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| m68hc05 microcontrollers mc68hc705c8a/d rev. 3, 3/2002 mc68hc705c8a mc68hsc705c8a technical data f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 0&+&&$2 5hy 7hfkqlfdo'dwd mc68hc705c8a mc68hsc705c8a technical data to provide the most up-to-date information, the revision of our documents on the world wide web will be the most current. your printed copy may be an earlier revision. to verify you have the latest information available, refer to: http://www. freescale.com the following revision history table summarizes changes contained in this document. for your convenience, the page number designators have been linked to the appropriate location. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 7hfkqlfdo'dwd 0&+&&$2 5hy technical data revision history date revision level description page number(s) may, 2001 2.1 1.7 pin functions ? added description of programming voltage (v pp ) pin 1.7.2 v pp 29 removed note following 1.7.11 port d i/o pins (pd7 and pd5?pd0) 33 14.2 introduction ? updated motorola contact information 192 march, 2002 3 14.7 44-pin quad flat pack (qfp) ? corrected case outline drawing from case #824e to case #824a 195 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc705c8a ? rev. 3 technical data motorola list of sections technical data ? mc68hc705c8a list of sections section 1. general description . . . . . . . . . . . . . . . . . . . . 21 section 2. memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 section 3. central processor unit (cpu) . . . . . . . . . . . . 43 section 4. interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 section 5. resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 section 6. low-power modes. . . . . . . . . . . . . . . . . . . . . . 69 section 7. parallel input/output (i/o). . . . . . . . . . . . . . . . 77 section 8. capture/compare timer . . . . . . . . . . . . . . . . . 89 section 9. eprom/otprom (prom) . . . . . . . . . . . . . . 103 section 10. serial communications interface (sci) . . . 121 section 11. serial peripheral interface (spi). . . . . . . . . 139 section 12. instruction set . . . . . . . . . . . . . . . . . . . . . . . 153 section 13. electrical specifications . . . . . . . . . . . . . . 171 section 14. mechanical specifications . . . . . . . . . . . . . 191 section 15. ordering information . . . . . . . . . . . . . . . . . 199 appendix a. mc68hsc705c8a . . . . . . . . . . . . . . . . . . . 201 index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data mc68hc705c8a ? rev. 3 6 list of sections list of sections f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc705c8a ? rev. 3 technical data motorola table of contents technical data ? mc68hc705c8a table of contents section 1. general description 1.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 1.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 1.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 1.4 programmable options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 1.5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 1.6 pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 1.7 pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 1.7.1 v dd and v ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 1.7.2 v pp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 1.7.3 osc1 and osc2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 1.7.4 external reset pin (reset ) . . . . . . . . . . . . . . . . . . . . . . . .32 1.7.5 external interrupt request pin (irq ) . . . . . . . . . . . . . . . . . . 32 1.7.6 input capture pin (tcap) . . . . . . . . . . . . . . . . . . . . . . . . . . 32 1.7.7 output compare pin (tcmp) . . . . . . . . . . . . . . . . . . . . . . . .33 1.7.8 port a i/o pins (pa7 ? pa0). . . . . . . . . . . . . . . . . . . . . . . . . . 33 1.7.9 port b i/o pins (pb7 ? pb0). . . . . . . . . . . . . . . . . . . . . . . . . . 33 1.7.10 port c i/o pins (pc7 ? pc0) . . . . . . . . . . . . . . . . . . . . . . . . . 33 1.7.11 port d i/o pins (pd7 and pd5 ? pd0) . . . . . . . . . . . . . . . . . . 33 section 2. memory 2.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.3 memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.4 input/output (i/o) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data mc68hc705c8a ? rev. 3 8 table of contents table of contents 2.5 ram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.6 eprom/otprom (prom) . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2.7 bootloader rom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 section 3. central processor unit (cpu) 3.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.3 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.3.1 accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.3.2 index register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.3.3 stack pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.3.4 program counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.3.5 condition code register . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3.4 arithmetic/logic unit (alu) . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 section 4. interrupts 4.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 4.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 4.3 interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 4.3.1 software interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 4.3.2 external interrupt (irq ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 4.3.3 port b interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 4.3.4 capture/compare timer interrupts . . . . . . . . . . . . . . . . . . .55 4.3.5 sci interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 4.3.6 spi interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 4.4 interrupt processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 section 5. resets 5.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 5.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents mc68hc705c8a ? rev. 3 technical data motorola table of contents 5.3 reset sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 5.3.1 power-on reset (por) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 5.3.2 external reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 5.3.3 programmable and non-programmable cop watchdog resets . . . . . . . . . . . . . . . . . . . . . . . . . . 62 5.3.4 clock monitor reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 section 6. low-power modes 6.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 6.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 6.3 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 6.3.1 sci during stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 6.3.2 spi during stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 6.3.3 programmable cop watchdog in stop mode . . . . . . . . . . .71 6.3.4 non-programmable cop watchdog in stop mode . . . . . . .73 6.4 wait mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 6.4.1 programmable cop watchdog in wait mode . . . . . . . . . . .75 6.4.2 non-programmable cop watchdog in wait mode . . . . . . .75 6.5 data-retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 section 7. parallel input/output (i/o) 7.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 7.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 7.3 port a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 7.3.1 port a data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 7.3.2 data direction register a. . . . . . . . . . . . . . . . . . . . . . . . . . . 79 7.3.3 port a logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 7.4 port b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 7.4.1 port b data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 7.4.2 data direction register b. . . . . . . . . . . . . . . . . . . . . . . . . . . 82 7.4.3 port b logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data mc68hc705c8a ? rev. 3 10 table of contents table of contents 7.5 port c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 7.5.1 port c data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 7.5.2 data direction register c. . . . . . . . . . . . . . . . . . . . . . . . . . . 86 7.5.3 port c logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 7.6 port d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 section 8. capture/compare timer 8.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 8.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 8.3 timer operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 8.3.1 input capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 8.3.2 output compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 8.4 timer i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 8.4.1 timer control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 8.4.2 timer status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 8.4.3 timer registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 8.4.4 alternate timer registers. . . . . . . . . . . . . . . . . . . . . . . . . . . 98 8.4.5 input capture registers . . . . . . . . . . . . . . . . . . . . . . . . . . 100 8.4.6 output compare registers. . . . . . . . . . . . . . . . . . . . . . . . . 101 section 9. eprom/otprom (prom) 9.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 9.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 9.3 eprom/otprom (prom) programming . . . . . . . . . . . . . . .104 9.3.1 program register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 9.3.2 preprogramming steps . . . . . . . . . . . . . . . . . . . . . . . . . . .110 9.4 prom programming routines . . . . . . . . . . . . . . . . . . . . . . . . 111 9.4.1 program and verify prom. . . . . . . . . . . . . . . . . . . . . . . . .111 9.4.2 verify prom contents . . . . . . . . . . . . . . . . . . . . . . . . . . . .112 9.4.3 secure prom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 9.4.4 secure prom and verify . . . . . . . . . . . . . . . . . . . . . . . . . .113 9.4.5 secure prom and dump. . . . . . . . . . . . . . . . . . . . . . . . . .113 9.4.6 load program into ram and execute . . . . . . . . . . . . . . . .114 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents mc68hc705c8a ? rev. 3 technical data motorola table of contents 9.4.7 execute program in ram. . . . . . . . . . . . . . . . . . . . . . . . . . 115 9.4.8 dump prom contents. . . . . . . . . . . . . . . . . . . . . . . . . . . .115 9.5 control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 9.5.1 option register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 9.5.2 mask option register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 9.5.3 mask option register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 9.6 eprom erasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 section 10. serial communications interface (sci) 10.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 10.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 10.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 10.4 sci data format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 10.5 sci operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123 10.5.1 transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123 10.5.2 receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 10.6 sci i/o registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 10.6.1 sci data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 10.6.2 sci control register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . .130 10.6.3 sci control register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . .131 10.6.4 sci status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 10.6.5 baud rate register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 section 11. serial peripheral interface (spi) 11.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 11.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 11.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 11.4 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 11.4.1 pin functions in master mode . . . . . . . . . . . . . . . . . . . . . .143 11.4.2 pin functions in slave mode . . . . . . . . . . . . . . . . . . . . . . .144 11.5 multiple-spi systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data mc68hc705c8a ? rev. 3 12 table of contents table of contents 11.6 serial clock polarity and phase . . . . . . . . . . . . . . . . . . . . . . .146 11.7 spi error conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 11.7.1 mode fault error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147 11.7.2 write collision error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 11.7.3 overrun error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 11.8 spi interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148 11.9 spi i/o registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 11.9.1 spi data register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 11.9.2 spi control register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 11.9.3 spi status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 section 12. instruction set 12.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 12.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 12.3 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 12.3.1 inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 12.3.2 immediate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 12.3.3 direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 12.3.4 extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 12.3.5 indexed, no offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 12.3.6 indexed, 8-bit offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 12.3.7 indexed, 16-bit offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 12.3.8 relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 12.4 instruction types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 12.4.1 register/memory instructions. . . . . . . . . . . . . . . . . . . . . . .158 12.4.2 read-modify-write instructions . . . . . . . . . . . . . . . . . . . . . 159 12.4.3 jump/branch instructions. . . . . . . . . . . . . . . . . . . . . . . . . . 160 12.4.4 bit manipulation instructions . . . . . . . . . . . . . . . . . . . . . . .162 12.4.5 control instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 12.5 instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 12.6 opcode map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents mc68hc705c8a ? rev. 3 technical data motorola table of contents section 13. electrical specifications 13.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 13.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 13.3 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 13.4 operating temperature range. . . . . . . . . . . . . . . . . . . . . . . .173 13.5 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 13.6 power considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 13.7 5.0-volt dc electrical characteristics. . . . . . . . . . . . . . . . . . .175 13.8 3.3-volt dc electrical characteristics . . . . . . . . . . . . . . . . . .176 13.9 5.0-volt control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 13.10 3.3-volt control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 13.11 5.0-volt serial peripheral interface (spi) timing . . . . . . . . . .185 13.12 3.3-volt serial peripheral interface (spi) timing . . . . . . . . . .187 section 14. mechanical specifications 14.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 14.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 14.3 40-pin plastic dual in-line package (pdip). . . . . . . . . . . . . .192 14.4 40-pin ceramic dual in-line package (cerdip) . . . . . . . . . . .193 14.5 44-lead plastic-leaded chip carrier (plcc) . . . . . . . . . . . .194 14.6 44-lead ceramic-leaded chip carrier (clcc) . . . . . . . . . . .195 14.7 44-pin quad flat pack (qfp). . . . . . . . . . . . . . . . . . . . . . . . . 196 14.8 42-pin shrink dual in-line package (sdip) . . . . . . . . . . . . . .197 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data mc68hc705c8a ? rev. 3 14 table of contents table of contents section 15. ordering information 15.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 15.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 15.3 mcu order numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .199 appendix a. mc68hsc705c8a a.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 a.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 a.3 5.0-volt high-speed dc electrical characteristics. . . . . . . . .202 a.4 3.3-volt high-speed dc electrical characteristics . . . . . . . .203 a.5 5.0-volt high-speed control timing . . . . . . . . . . . . . . . . . . . .204 a.6 3.3-volt high-speed control timing . . . . . . . . . . . . . . . . . . . .204 a.7 5.0-volt high-speed spi timing . . . . . . . . . . . . . . . . . . . . . .205 a.8 3.3-volt high-speed spi timing. . . . . . . . . . . . . . . . . . . . . . .207 a.9 ordering information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 index index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc705c8a ? rev. 3 technical data motorola list of figures technical data ? mc68hc705c8a list of figures figure title page 1-1 option register (option) . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 1-2 mc68hc705c8a block diagram . . . . . . . . . . . . . . . . . . . . . 25 1-3 40-pin pdip/cerdip pin assignments . . . . . . . . . . . . . . . . . 26 1-4 44-lead plcc/clcc pin assignments . . . . . . . . . . . . . . . . 27 1-5 44-pin qfp pin assignments. . . . . . . . . . . . . . . . . . . . . . . .27 1-6 42-pin sdip pin assignments . . . . . . . . . . . . . . . . . . . . . . . 28 1-7 bypassing layout recommendation . . . . . . . . . . . . . . . . . . 29 1-8 crystal connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 1-9 2-pin ceramic resonator connections . . . . . . . . . . . . . . . . 31 1-10 3-pin ceramic resonator connections . . . . . . . . . . . . . . . .31 1-11 external clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2-1 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 2-2 i/o register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3-1 programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .044 3-2 accumulator (a) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 045 3-3 index register (x) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 045 3-4 stack pointer (sp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 046 3-5 program counter (pc) . . . . . . . . . . . . . . . . . . . . . . . . . . . .046 3-6 condition code register (ccr) . . . . . . . . . . . . . . . . . . . . . 047 4-1 external interrupt internal function diagram . . . . . . . . . . . .52 4-2 external interrupt timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 4-3 port b i/o logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 4-4 interrupt stacking order . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 4-5 reset and interrupt processing flowchart . . . . . . . . . . . . . .59 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data mc68hc705c8a ? rev. 3 16 list of figures list of figures figure title page 5-1 programmable cop watchdog diagram . . . . . . . . . . . . . . .63 5-2 programmable cop reset register (coprst) . . . . . . . . . 64 5-3 programmable cop control register (copcr) . . . . . . . . . 64 5-4 non-programmable cop watchdog diagram . . . . . . . . . . .67 6-1 stop/wait mode function flowchart . . . . . . . . . . . . . . . . . .70 6-2 programmable cop watchdog in stop mode (pcope = 1) flowchart. . . . . . . . . . . . . . .72 6-3 non-programmable cop watchdog in stop mode (ncope = 1) flowchart . . . . . . . . . . . . . .74 7-1 port a data register (porta). . . . . . . . . . . . . . . . . . . . . . . 78 7-2 data direction register a (ddra) . . . . . . . . . . . . . . . . . . . .79 7-3 port a i/o logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 7-4 port b data register (portb). . . . . . . . . . . . . . . . . . . . . . . 81 7-5 data direction register b (ddrb) . . . . . . . . . . . . . . . . . . . .82 7-6 port b i/o logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 7-7 port c data register (portc) . . . . . . . . . . . . . . . . . . . . . . 85 7-8 data direction register c (ddrc) . . . . . . . . . . . . . . . . . . . .86 7-9 port c i/o logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 7-10 port d fixed input register (portd) . . . . . . . . . . . . . . . . .88 8-1 timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 8-2 timer i/o register summary . . . . . . . . . . . . . . . . . . . . . . . .91 8-3 input capture operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 8-4 output compare operation . . . . . . . . . . . . . . . . . . . . . . . . . 93 8-5 timer control register (tcr) . . . . . . . . . . . . . . . . . . . . . . . 94 8-6 timer status register (tsr) . . . . . . . . . . . . . . . . . . . . . . . .96 8-7 timer registers (trh and trl) . . . . . . . . . . . . . . . . . . . . . 97 8-8 timer register reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 8-10 alternate timer register reads . . . . . . . . . . . . . . . . . . . . . .99 8-9 alternate timer registers (atrh and atrl) . . . . . . . . . . . 99 8-11 input capture registers (icrh and icrl) . . . . . . . . . . . . . 100 8-12 output compare registers (ocrh and ocrl). . . . . . . . .101 9-1 eprom/otprom programming flowchart . . . . . . . . . . .105 9-2 prom programming circuit . . . . . . . . . . . . . . . . . . . . . . . . 106 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . list of figures mc68hc705c8a ? rev. 3 technical data motorola list of figures figure title page 9-3 program register (prog) . . . . . . . . . . . . . . . . . . . . . . . . . 109 9-4 option register (option) . . . . . . . . . . . . . . . . . . . . . . . . . . 116 9-5 mask option register 1 (mor1) . . . . . . . . . . . . . . . . . . . . 117 9-6 mask option register 2 (mor2) . . . . . . . . . . . . . . . . . . . . 118 10-1 sci data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123 10-2 sci transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 10-3 sci transmitter i/o register summary . . . . . . . . . . . . . . .125 10-4 sci receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 10-5 sci data register (scdr). . . . . . . . . . . . . . . . . . . . . . . . . 129 10-6 sci control register 1 (sccr1) . . . . . . . . . . . . . . . . . . . . 130 10-7 sci control register 2 (sccr2) . . . . . . . . . . . . . . . . . . . . 131 10-8 sci status register (scsr) . . . . . . . . . . . . . . . . . . . . . . .133 10-9 baud rate register (baud) . . . . . . . . . . . . . . . . . . . . . . . .136 11-1 spi block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 11-2 spi i/o register summary . . . . . . . . . . . . . . . . . . . . . . . . . 142 11-3 master/slave connections . . . . . . . . . . . . . . . . . . . . . . . . .143 11-4 one master and three slaves block diagram . . . . . . . . . .145 11-5 two master/slaves and three slaves block diagram . . . .146 11-6 spi clock/data timing . . . . . . . . . . . . . . . . . . . . . . . . . . . .146 11-7 spi data register (spdr) . . . . . . . . . . . . . . . . . . . . . . . . . 149 11-8 spi control register (spcr) . . . . . . . . . . . . . . . . . . . . . . .149 11-9 spi status register (spsr) . . . . . . . . . . . . . . . . . . . . . . . . 151 13-1 equivalent test load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 13-2 typical voltage compared to current . . . . . . . . . . . . . . . .177 13-3 typical current versus internal frequency for run and wait modes . . . . . . . . . . . . . . .179 13-4 total current drain versus frequency . . . . . . . . . . . . . . . .180 13-5 timer relationships . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 13-6 stop recovery timing diagram . . . . . . . . . . . . . . . . . . . . .183 13-7 power-on reset and external reset timing diagram. . . .184 13-8 spi master timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 13-9 spi slave timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data mc68hc705c8a ? rev. 3 18 list of figures list of figures figure title page 14-1 mc68hc705c8ap package dimensions (case #711). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 14-2 mc68hc705c8as package dimensions (case #734a) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .193 14-3 mc68hc705c8afn package dimensions (case #777). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 14-4 mc68hc705c8afs package dimensions (case #777b) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .195 14-5 mc68hc705c8afb package dimensions (case #824a) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .196 14-6 mc68hc705c8ab package dimensions (case #858). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc705c8a ? rev. 3 technical data motorola list of tables technical data ? mc68hc705c8a list of tables table title page 2-1 memory configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 4-1 reset/interrupt vector addresses . . . . . . . . . . . . . . . . . . . . . 57 5-1 programmable cop timeout period selection . . . . . . . . . . .66 7-1 port a pin functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 7-2 port b pin functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 7-3 port c pin functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 9-1 mc68hc05pgmr pcb reference designators . . . . . . . . .104 9-2 prom programming routines . . . . . . . . . . . . . . . . . . . . . . .108 10-1 baud rate generator clock prescaling . . . . . . . . . . . . . . . . 136 10-2 baud rate selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 10-3 baud rate selection examples . . . . . . . . . . . . . . . . . . . . . . 138 11-1 spi clock rate selection . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 12-1 register/memory instructions. . . . . . . . . . . . . . . . . . . . . . . . 158 12-2 read-modify-write instructions . . . . . . . . . . . . . . . . . . . . . .159 12-3 jump and branch instructions . . . . . . . . . . . . . . . . . . . . . . .161 12-4 bit manipulation instructions. . . . . . . . . . . . . . . . . . . . . . . . . 162 12-5 control instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 12-6 instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . .164 12-7 opcode map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170 15-1 mc68hc705c8a order numbers . . . . . . . . . . . . . . . . . . . .199 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data mc68hc705c8a ? rev. 3 20 list of tables list of tables table title page a-1 programmable cop timeout period selection . . . . . . . . . . .202 a-2 mc68hsc705c8a order numbers . . . . . . . . . . . . . . . . . . . . 209 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc705c8a ? rev. 3 technical data motorola general description technical data ? mc68hc705c8a section 1. general description 1.1 contents 1.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 1.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 1.4 programmable options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 1.5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 1.6 pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 1.7 pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 1.7.1 v dd and v ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 1.7.2 v pp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 1.7.3 osc1 and osc2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 1.7.3.1 crystal resonator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 1.7.3.2 ceramic resonator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 1.7.3.3 external clock signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 1.7.4 external reset pin (reset ) . . . . . . . . . . . . . . . . . . . . . . . .32 1.7.5 external interrupt request pin (irq ) . . . . . . . . . . . . . . . . . . 32 1.7.6 input capture pin (tcap) . . . . . . . . . . . . . . . . . . . . . . . . . . 32 1.7.7 output compare pin (tcmp) . . . . . . . . . . . . . . . . . . . . . . . .33 1.7.8 port a i/o pins (pa7 ? pa0). . . . . . . . . . . . . . . . . . . . . . . . . . 33 1.7.9 port b i/o pins (pb7 ? pb0). . . . . . . . . . . . . . . . . . . . . . . . . . 33 1.7.10 port c i/o pins (pc7 ? pc0) . . . . . . . . . . . . . . . . . . . . . . . . . 33 1.7.11 port d i/o pins (pd7 and pd5 ? pd0) . . . . . . . . . . . . . . . . . . 33 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data mc68hc705c8a ? rev. 3 22 general description general description 1.2 introduction the mc68hc705c8a, an enhanced version of the mc68hc705c8, is a member of the low-cost, high-performance m68hc05 family of 8-bit microcontroller units (mcu). the mc68hsc705c8a, introduced in appendix a. mc68hsc705c8a , is an enhanced, high-speed version of the mc68hc705c8a. the m68hc05 family is based on the customer-specified integrated circuit (csic) design strategy. all mcus in the family use the m68hc05 central processor unit (cpu) and are available with a variety of subsystems, memory sizes and types, and package types. 1.3 features features of the mc68hc705c8a include: m68hc05 central processor unit (cpu) on-chip oscillator with crystal/ceramic resonator memory-mapped input/output (i/o) selectable memory configurations selectable programmable and/or non-programmable computer operating properly (cop) watchdog timers selectable port b external interrupt capability clock monitor high current drive on pin c7 (pc7) 24 bidirectional i/o lines and 7 input-only lines serial communications interface (sci) system serial peripheral interface (spi) system bootstrap capability power-saving stop, wait, and data-retention modes single 3.0-volt to 5.5-volt supply (2-volt data-retention mode) fully static operation f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general description programmable options mc68hc705c8a ? rev. 3 technical data motorola general description software-programmable external interrupt sensitivity bidirectional reset pin note: a line over a signal name indicates an active low signal. for example, reset is active high and reset is active low. any reference to voltage, current, or frequency specified in this document will refer to the nominal values. the exact values and their tolerance or limits are specified in section 13. electrical specifications . 1.4 programmable options these options are programmable in the mask option registers: enabling of port b pullup devices (see 9.5.2 mask option register 1 ) enabling of non-programmable cop watchdog (see 9.5.3 mask option register 2 ) these options are programmable in the option register (see figure 1-1 ): one of four selectable memory configurations programmable read-only memory (prom) security 1 external interrupt sensitivity 1. no security feature is absolutely secure. however, motorola ? s strategy is to make reading or copying the prom difficult for unauthorized users. address: $1fdf bit 7654321bit 0 read: ram0 ram1 0 0 sec * irq 0 write: reset:0000 * u10 * implemented as an eprom cell = unimplemented u = unaffected figure 1-1. option register (option) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data mc68hc705c8a ? rev. 3 24 general description general description ram0 ? random-access memory control bit 0 1 = maps 32 bytes of ram into page zero starting at address $0030. addresses from $0020 to $002f are reserved. this bit can be read or written at any time, allowing memory configuration to be changed during program execution. 0 = provides 48 bytes of prom at location $0020 ? $005f. ram1 ? random-access memory control bit 1 1 = maps 96 bytes of ram into page one starting at address $0100. this bit can be read or written at any time, allowing memory configuration to be changed during program execution. 0 = provides 96 bytes of prom at location $0100. sec ? security bit this bit is implemented as an erasable, programmable read-only memory (eprom) cell and is not affected by reset. 1 = bootloader disabled; mcu operates only in single-chip mode 0 = security off; bootloader can be enabled irq ? interrupt request pin sensitivity bit irq is set only by reset, but can be cleared by software. this bit can be written only once. 1 = irq pin is both negative edge- and level-sensitive. 0 = irq pin is negative edge-sensitive only. bits 5, 4, and 0 ? not used; always read 0 bit 2 ? unaffected by reset; reads either 1 or 0 1.5 block diagram figure 1-2 shows the structure of the mc68hc705c8a. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general description block diagram mc68hc705c8a ? rev. 3 technical data motorola general description figure 1-2. mc68hc705c8a block diagram internal processor clock tcap 2 accumulator index register osc1 osc2 oscillator irq reset cop watchdog cpu m68hc05 cpu arithmetic v dd v ss cpu registers control port a data direction a pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 power option eprom/otprom ? 7744 bytes 1 1 0 0 0 0 0 c z n i h 1 1 1 16-bit capture/compare port b data direction b pb0 * pb1 * pb2 * pb3 * pb4 * pb5 * pb6 * pb7 * port c data direction c pc0 pc1 pc2 pc3 pc4 pc5 pc6 pc7? timer system baud rate generator pd7 rdi (pd0) tdo (pd1) miso (pd2) mosi (pd3) sck (pd4) ss (pd5) sci spi tcmp ram ? 176 bytes register boot rom ? 240 bytes (144 bytes configurable) program register eprom programming v pp and clock monitor port d logic unit (304 bytes maximum) control program counter stack pointer condition code register * port b pins also function as external interrupts. ? pc7 has a high current sink and source capability. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data mc68hc705c8a ? rev. 3 26 general description general description 1.6 pin assignments the mc68hc705c8a is available in six packages: 40-pin plastic dual in-line package (pdip) 40-pin ceramic dual in-line package (cerdip) 44-lead plastic-leaded chip carrier (plcc) 44-lead ceramic-leaded chip carrier (clcc) 44-pin quad flat pack (qfp) 42-pin shrink dual in-line package (sdip) the pin assignments for these packages are shown in figure 1-3 , figure 1-4 , figure 1-5 , and figure 1-6 . figure 1-3. 40-pin pdip/cerdip pin assignments 1 2 3 4 5 6 7 8 9 10 11 12 13 14 27 28 29 30 31 32 33 34 35 36 37 38 39 40 v dd osc1 osc2 tcap pd7 tcmp pd5/ss pd4/sck pd3/mosi pd2/miso pd1/tdo pd0/rdi pc0 pc1 reset irq v pp pa7 pa5 pa4 pa3 pa2 pa1 pa0 pb0 pb1 pb2 pa6 15 16 17 18 19 20 pb4 pb5 pb6 pb7 v ss pb3 21 22 23 24 25 26 pc2 pc3 pc4 pc5 pc6 pc7 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general description pin assignments mc68hc705c8a ? rev. 3 technical data motorola general description figure 1-4. 44-lead plcc/clcc pin assignments figure 1-5. 44-pin qfp pin assignments pa6 pa7 v pp nc irq reset v dd osc1 osc2 tcap nc 6 5 4 3 2 1 44 43 42 41 40 39 38 37 pd7 tcmp pd5/ss 36 35 pd4/sck pd3/mosi 34 pd2/miso 33 pd1/tdo 32 pd0/rdi 31 pc0 30 pc1 29 pc2 28 27 26 25 24 23 22 21 20 19 18 nc pb5 pb6 pb7 v ss nc pc7 pc6 pc5 pc4 pc3 pb4 pb3 pb2 pb1 17 16 15 14 pb0 pa0 pa1 pa2 13 12 11 10 pa3 9 pa4 8 pa5 7 pd7 tcap osc2 osc1 v dd nc nc reset irq v pp pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 pb0 pb1 pb2 pb3 pd3/mosi pd2/miso pd4/sck pd5/ss tcmp pd1/tdo pd0/rdi pc0 pc1 pc2 pc3 nc pc4 pc5 pc6 pc7 v ss nc pb7 pb6 pb5 pb4 1 234567891011 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data mc68hc705c8a ? rev. 3 28 general description general description figure 1-6. 42-pin sdip pin assignments v pp pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 pb0 pb1 pb2 pb3 nc pb4 pb5 pb6 v ss v dd osc1 osc2 tcap pd7 tcmp pd5/ss pd4/sck pd3/mosi pd2/miso pd1/tdo pd0/rdi pc0 pc1 pc2 nc pc3 pc4 pc5 pc6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 pc7 pb7 21 reset irq f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general description pin functions mc68hc705c8a ? rev. 3 technical data motorola general description 1.7 pin functions this subsection describes the mc68hc705c8a signals. reference is made, where applicable, to other sections that contain more detail about the function being performed. 1.7.1 v dd and v ss v dd and v ss are the power supply and ground pins. the mcu operates from a single power supply. very fast signal transitions occur on the mcu pins, placing high short-duration current demands on the power supply. to prevent noise problems, take special care to provide good power supply bypassing at the mcu. place bypass capacitors as close to the mcu as possible, as shown in figure 1-7 . 1.7.2 v pp this pin provides the programming voltage to the eprom array. for normal operation, v pp shuld be tied to v dd . note: connecting the v pp pin (programming voltage) to v ss (ground) could result in damage to the mcu. mcu c2 v dd v ss v+ + c1 figure 1-7. bypassing layout recommendation f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data mc68hc705c8a ? rev. 3 30 general description general description 1.7.3 osc1 and osc2 the osc1 and osc2 pins are the control connections for the 2-pin on-chip oscillator. the oscillator can be driven by: crystal resonator ceramic resonator external clock signal note: the frequency of the internal oscillator is f osc . the mcu divides the internal oscillator output by two to produce the internal clock with a frequency of f op . 1.7.3.1 crystal resonator the circuit in figure 1-8 shows a crystal oscillator circuit for an at-cut, parallel resonant crystal. follow the crystal supplier ? s recommendations, because the crystal parameters determine the external component values required to provide reliable startup and maximum stability. the load capacitance values used in the oscillator circuit design should account for all stray layout capacitances. to minimize output distortion, mount the crystal and capacitors as close as possible to the pins. note: use an at-cut crystal and not a strip or tuning fork crystal. the mcu might overdrive or have the incorrect characteristic impedance for a strip or tuning fork crystal. mcu osc1 osc2 xtal 22 pf 22 pf 10 m 2 mhz figure 1-8. crystal connections starting value only. follow crystal supplier ? s recommendations regarding component values that will provide reliable startup and maximum stability. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general description pin functions mc68hc705c8a ? rev. 3 technical data motorola general description 1.7.3.2 ceramic resonator to reduce cost, use a ceramic resonator instead of a crystal. use the circuit shown in figure 1-9 for a 2-pin ceramic resonator or the circuit shown in figure 1-10 for a 3-pin ceramic resonator, and follow the resonator manufacturer ? s recommendations. the external component values required for maximum stability and reliable starting depend upon the resonator parameters. the load capacitance values used in the oscillator circuit design should include all stray layout capacitances. to minimize output distortion, mount the resonator and capacitors as close as possible to the pins. note: the bus frequency (f op ) is one-half the external or crystal frequency (f osc ), while the processor clock cycle (t cyc ) is two times the f osc period. mcu osc1 osc2 ceramic cc r resonator figure 1-9. 2-pin ceramic resonator connections . mcu osc1 osc2 ceramic resonator figure 1-10. 3-pin ceramic resonator connections f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data mc68hc705c8a ? rev. 3 32 general description general description 1.7.3.3 external clock signal an external clock from another cmos-compatible device can drive the osc1 input, with the osc2 pin unconnected, as figure 1-11 shows. note: the bus frequency (f op ) is one-half the external frequency (f osc ) while the processor clock cycle is two times the f osc period. 1.7.4 external reset pin (reset ) a logic 0 on the bidirectional reset pin forces the mcu to a known startup state. the reset pin contains an internal schmitt trigger as part of its input to improve noise immunity. see section 5. resets . 1.7.5 external interrupt request pin (irq ) the irq pin is an asynchronous external interrupt pin. the irq pin contains an internal schmitt trigger as part of its input to improve noise immunity. see 4.3.2 external interrupt (irq) . 1.7.6 input capture pin (tcap) the tcap pin is the input capture pin for the on-chip capture/compare timer. the tcap pin contains an internal schmitt trigger as part of its input to improve noise immunity. see section 8. capture/compare timer . mcu osc1 osc2 external cmos clock figure 1-11. external clock f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general description pin functions mc68hc705c8a ? rev. 3 technical data motorola general description 1.7.7 output compare pin (tcmp) the tcmp pin is the output compare pin for the on-chip capture/compare timer. see section 8. capture/compare timer . 1.7.8 port a i/o pins (pa7 ? pa0) these eight i/o lines comprise port a, a general-purpose, bidirectional i/o port. the pins are programmable as either inputs or outputs under software control of the data direction registers. see 7.3 port a . 1.7.9 port b i/o pins (pb7 ? pb0) these eight i/o pins comprise port b, a general-purpose, bidirectional i/o port. the pins are programmable as either inputs or outputs under software control of the data direction registers. port b pins also can be configured to function as external interrupts. see 7.4 port b . 1.7.10 port c i/o pins (pc7 ? pc0) these eight i/o pins comprise port c, a general-purpose, bidirectional i/o port. the pins are programmable as either inputs or outputs under software control of the data direction registers. pc7 has a high current sink and source capability. see 7.5 port c . 1.7.11 port d i/o pins (pd7 and pd5 ? pd0) these seven lines comprise port d, a fixed input port. all special functions that are enabled (spi and sci) affect this port. see 7.6 port d . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data mc68hc705c8a ? rev. 3 34 general description general description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc705c8a ? rev. 3 technical data motorola memory technical data ? mc68hc705c8a section 2. memory 2.1 contents 2.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.3 memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.4 input/output (i/o) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.5 ram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.6 eprom/otprom (prom) . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2.7 bootloader rom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2.2 introduction this section describes the organization of the on-chip memory. 2.3 memory map the central processor unit (cpu) can address eight kbytes of memory and input/output (i/o) registers. the program counter typically advances one address at a time through memory, reading the program instructions and data. the programmable read-only memory (prom) portion of memory ? either one-time programmable read-only memory (otprom) or erasable, programmable read-only memory (eprom) ? holds the program instructions, fixed data, user-defined vectors, and interrupt service routines. the random-access memory (ram) portion of memory holds variable data. i/o registers are memory-mapped so that the cpu can access their locations in the same way that it accesses all other memory locations. the shared stack area is used during processing of an interrupt or f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data mc68hc705c8a ? rev. 3 36 memory memory subroutine call to save the cpu state. the stack pointer decrements during pushes and increments during pulls. figure 2-1 is a memory map of the mcu. addresses $0000 ? $001f, shown in figure 2-2 , contain most of the control, status, and data registers. additional i/o registers have these addresses: $1fdf, option register $1ff0, mask option register 1 (mor1) $1ff1, mask option register 2 (mor2) 2.4 input/output (i/o) the first 32 addresses of memory space, from $0000 to $001f, are the i/o section. these are the addresses of the i/o control registers, status registers, and data registers. see figure 2-2 for more information. 2.5 ram one of four selectable memory configurations is selected by the state of the ram1 and ram0 bits in the option register located at $1fdf. reset or power-on reset (por) clears these bits, automatically selecting the first memory configuration as shown in table 2-1 . see 9.5.1 option register . note: be careful when using nested subroutines or multiple interrupt levels. the cpu can overwrite data in the stack ram during a subroutine or during the interrupt stacking operation. table 2-1. memory configurations ram0 ram1 ram bytes prom bytes 0 0 176 7744 1 0 208 7696 0 1 272 7648 1 1 304 7600 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory eprom/otprom (prom) mc68hc705c8a ? rev. 3 technical data motorola memory 2.6 eprom/otprom (prom) an mcu with a quartz window has a maximum of 7744 bytes of eprom. the quartz window allows the eprom erasure with ultraviolet light. in an mcu without a quartz window, the eprom cannot be erased and serves a maximum 7744 bytes of otprom (see table 2-1 ). see section 9. eprom/otprom (prom) . 2.7 bootloader rom the 240 bytes at addresses $1f00 ? $1fef are reserved rom addresses that contain the instructions for the bootloader functions. see section 9. eprom/otprom (prom) . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data mc68hc705c8a ? rev. 3 38 memory memory figure 2-1. memory map $0000 i/o registers 32 bytes port a data register $0000 port b data register $0001 $001f port c data register $0002 $0020 unused 16 bytes user prom 48 bytes port d fixed input port $0003 port a data direction register $0004 $002f port b data direction register $0005 $0030 ram 32 bytes port c data direction register $0006 unused $0007 unused $0008 $004f ram0 = 1 (1) ram0 = 0 (1) unused $0009 $0050 spi control register $000a spi status register $000b $00bf spi data register $000c $00c0 stack 64 bytes sci baud rate register $000d sci control register 1 $000e $00ff sci control register 2 $000f $0100 user prom 96 bytes ram 96 bytes sci status register $0010 sci data register $0011 timer control register $0012 timer status register $0013 input capture register (high) $0014 input capture register (low) $0015 output compare register (high) $0016 output compare register (low) $0017 $015f ram1 = 0 (1) ram1 = 1 (1) timer register (high) $0018 $0160 user prom 7584 bytes timer register (low) $0019 alternate timer register (high) $001a $1eff alternate timer register (low) $001b $1f00 bootloader rom 240 bytes eprom program register $001c cop reset register $001d $1fde cop control register $001e $1fdf option register unused $001f $1fe0 $1fef boot rom vectors 16 bytes $1ff0 mask option register 1 reserved $1ff2 reserved $1ff3 $1ff1 mask option register 2 spi interrupt vector (high) $1ff4 spi interrupt vector (low) $1ff5 $1ff2 user prom vectors 12 bytes sci interrupt vector (high) $1ff6 sci interrupt vector (low) $1ff7 $1fff timer interrupt vector (high) $1ff8 timer interrupt vector (low) $1ff9 external interrupt vector (high) $1ffa (1 ) see 9.5.1 option register for information. external interrupt vector (low) $1ffb software interrupt vector (high) $1ffc software interrupt vector (low) $1ffd reset vector (high) $1ffe reset vector (low) $1fff ram 176 bytes f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory bootloader rom mc68hc705c8a ? rev. 3 technical data motorola memory addr. register name bit 7 6 5 4 3 2 1 bit 0 $0000 port a data register (porta) see page 78. read: pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 write: reset: unaffected by reset $0001 port b data register (portb) see page 81. read: pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 write: reset: unaffected by reset $0002 port c data register (portc) see page 85. read: pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 write: reset: unaffected by reset $0003 port d fixed input register (portd) see page 88. read: pd7 ss sck mosi miso tdo rdi write: reset: unaffected by reset $0004 port a data direction register (ddra) see page 79. read: ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 write: reset: 0 0 0 0 0 0 0 0 $0005 port b data direction register (ddrb) see page 82. read: ddrb7 ddrb6 ddrb5 ddrb4 ddrb3 ddrb2 ddrb1 ddrb0 write: reset: 0 0 0 0 0 0 0 0 $0006 port c data direction (ddrc) see page 86. read: ddrc7 ddrc6 ddrc5 ddrc4 ddrc3 ddrc2 ddrc1 ddrc0 write: reset: 0 0 0 0 0 0 0 0 $0007 unimplemented $0008 unimplemented $0009 unimplemented = unimplemented u = unaffected figure 2-2. i/o register summary (sheet 1 of 4) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data mc68hc705c8a ? rev. 3 40 memory memory $000a spi control register (spcr) see page 149. read: spie spe mstr cpol cpha spr1 spr0 write: reset: 0 0 0 u u u u $000b spi status register (spsr) see page 151. read: spif wcol modf write: reset: 0 0 0 $000c spi data register (spdr) see page 149. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: unaffected by reset $000d baud rate register (baud) see page 136. read: scp1 scp0 scr2 scr1 scr0 write: reset: u u 0 0 u u u u $000e sci control register 1 (sccr1) see page 130. read: r8 t8 m wake write: reset: u u u u $000f sci control register 2 (sccr2) see page 131. read: tie tcie rie ilie te re rwu sbk write: reset: 0 0 0 0 0 0 0 0 $0010 sci status register (scsr) see page 133. read: tdre tc rdrf idle or nf fe write: reset: 1 1 0 0 0 0 0 u $0011 sci data register (scdr) see page 129. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: unaffected by reset $0012 timer control register (tcr) see page 94. read: icie ocie toie 0 0 0 iedg olvl write: reset: 0 0 0 0 0 0 u 0 addr. register name bit 7 6 5 4 3 2 1 bit 0 = unimplemented u = unaffected figure 2-2. i/o register summary (sheet 2 of 4) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory bootloader rom mc68hc705c8a ? rev. 3 technical data motorola memory $0013 timer status register (tsr) see page 96. read: icf ocf tof 0 0 0 0 0 write: reset: u u u 0 0 0 0 0 $0014 input capture register high (icrh) see page 100. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: unaffected by reset $0015 input capture register low (icrl) see page 100. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: unaffected by reset $0016 output compare register high (ocrh) see page 101. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: unaffected by reset $0017 output compare register low (ocrl) see page 101. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: unaffected by reset $0018 timer register high (trh) see page 97. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: reset initializes trh to $ff $0019 timer register low (trl) see page 97. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: reset initializes trl to $fc $001a alternate timer register high (atrh) see page 99. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: reset initializes atrh to $ff $001b alternate timer register low (atrl) see page 99. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: reset initializes atrl to $fc addr. register name bit 7 6 5 4 3 2 1 bit 0 = unimplemented u = unaffected figure 2-2. i/o register summary (sheet 3 of 4) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data mc68hc705c8a ? rev. 3 42 memory memory $001c eprom programming register (prog) see page 109. read: 00 0 0 0 lat0pgm write: reset: 0 0 0 0 0 0 0 0 $001d programmable cop reset register (coprst) see page 64. read: write: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset: u u u u u u u u $001e programmable cop control register (copcr) see page 64. read: 0 0 0 copf cme pcope cm1 cm0 write: reset: 0 0 0 u 0 0 0 0 $001f unimplemented $1fdf option register (option) see page 116. read: ram0 ram1 0 0 sec * irq 0 write: reset: 0 0 0 0 * u10 * implemented as an eprom cell $1ff0 mask option register 1 (mor1) see page 117. read: pbpu7 pbpu6 pbpu5 pbpu4 pbpu3 pbpu2 pbpu1 pbpu0/ copc write: reset: unaffected by reset $1ff1 mask option register 2 (mor2) see page 118. read: ncope write: reset: unaffected by reset addr. register name bit 7 6 5 4 3 2 1 bit 0 = unimplemented u = unaffected figure 2-2. i/o register summary (sheet 4 of 4) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc705c8a ? rev. 3 technical data motorola central processor unit (cpu) technical data ? mc68hc705c8a section 3. central processor unit (cpu) 3.1 contents 3.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.3 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.3.1 accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.3.2 index register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.3.3 stack pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.3.4 program counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.3.5 condition code register . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3.4 arithmetic/logic unit (alu) . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.2 introduction this section describes the central processor unit (cpu) registers. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data mc68hc705c8a ? rev. 3 44 central processor unit (cpu) central processor unit (cpu) 3.3 cpu registers figure 3-1 shows the five cpu registers. these are hard-wired registers within the cpu and are not part of the memory map. figure 3-1. programming model accumulator (a) index register (x) 11 00 00 0 zc in 1h 11 bit 0 4 bit 7 5 condition code register (ccr) program counter (pc) stack pointer (sp) half-carry flag interrupt mask negative flag zero flag carry/borrow flag 6 321 bit 0 4 75 6 321 bit 0 4 75 6 321 bit 0 4 bit 7 5 6 321 bit 0 4 bit 7 5 6 321 8 bit 12 11 10 9 8 bit 12 11 10 9 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) cpu registers mc68hc705c8a ? rev. 3 technical data motorola central processor unit (cpu) 3.3.1 accumulator the accumulator (a) shown in figure 3-2 is a general-purpose 8-bit register. the cpu uses the accumulator to hold operands and results of arithmetic and non-arithmetic operations. figure 3-2. accumulator (a) 3.3.2 index register in the indexed addressing modes, the cpu uses the byte in the index register (x) shown in figure 3-3 to determine the conditional address of the operand. see 12.3.5 indexed, no offset , 12.3.6 indexed, 8-bit offset , and 12.3.7 indexed, 16-bit offset for more information on indexed addressing. the 8-bit index register also can serve as a temporary data storage location. figure 3-3. index register (x) bit 7654321bit 0 read: write: reset: unaffected by reset bit 7654321bit 0 read: write: reset: unaffected by reset f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data mc68hc705c8a ? rev. 3 46 central processor unit (cpu) central processor unit (cpu) 3.3.3 stack pointer the stack pointer (sp) shown in figure 3-4 is a 13-bit register that contains the address of the next free location on the stack. during a reset or after the reset stack pointer (rsp) instruction, the stack pointer initializes to $00ff. the address in the stack pointer decrements as data is pushed onto the stack and increments as data is pulled from the stack. the seven most significant bits of the stack pointer are fixed permanently at 0000011, so the stack pointer produces addresses from $00c0 to $00ff. if subroutines and interrupts use more than 64 stack locations, the stack pointer wraps around to address $00ff and begins writing over the previously stored data. a subroutine uses two stack locations. an interrupt uses five locations. figure 3-4. stack pointer (sp) 3.3.4 program counter the program counter (pc) shown in figure 3-5 is a 13-bit register that contains the address of the next instruction or operand to be fetched. normally, the address in the program counter automatically increments to the next sequential memory location every time an instruction or operand is fetched. jump, branch, and interrupt operations load the program counter with an address other than that of the next sequential location. bit 121110987654321bit 0 read: 0 000011 write: reset:0 000011111111 = unimplemented bit 121110987654321bit 0 read: write: reset: loaded with reset vector from $1ffe and $1fff figure 3-5. program counter (pc) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) cpu registers mc68hc705c8a ? rev. 3 technical data motorola central processor unit (cpu) 3.3.5 condition code register the condition code register (ccr) shown in figure 3-6 is an 8-bit register whose three most significant bits are permanently fixed at 111. the condition code register contains the interrupt mask and four bits that indicate the results of prior instructions. h ? half-carry bit the cpu sets the half-carry flag when a carry occurs between bits 3 and 4 of the accumulator during an add without carry (add) or add with carry (adc) operation. the half-carry bit is required for binary-coded decimal (bcd) arithmetic operations. reset has no affect on the half-carry flag. i ? interrupt mask bit setting the interrupt mask (i) disables interrupts. if an interrupt request occurs while the interrupt mask is a logic 0, the cpu saves the cpu registers on the stack, sets the interrupt mask, and then fetches the interrupt vector. if an interrupt request occurs while the interrupt mask is set, the interrupt request is latched. the cpu processes the latched interrupt as soon as the interrupt mask is cleared again. a return-from-interrupt (rti) instruction pulls the cpu registers from the stack, restoring the interrupt mask to its cleared state. after a reset, the interrupt mask is set and can be cleared only by a cli, stop, or wait instruction. bit 7654321bit 0 read: 1 1 1 hinzc write: reset:1 1 1u1uuu = unimplemented u = unaffected figure 3-6. condition code register (ccr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data mc68hc705c8a ? rev. 3 48 central processor unit (cpu) central processor unit (cpu) n ? negative flag the cpu sets the negative flag when an arithmetic operation, logical operation, or data manipulation produces a negative result (bit 7 in the results is a logic 1). reset has no effect on the negative flag. z ? zero flag the cpu sets the zero flag when an arithmetic operation, logical operation, or data manipulation produces a result of $00. reset has no effect on the zero flag. c ? carry/borrow flag the cpu sets the carry/borrow flag when an addition operation produces a carry out of bit 7 of the accumulator or when a subtraction operation requires a borrow. some logical operations and data manipulation instructions also clear or set the carry/borrow bit. reset has no effect on the carry/borrow flag. 3.4 arithmetic/logic unit (alu) the arithmetic/logic unit (alu) performs the arithmetic and logical operations defined by the instruction set. the binary arithmetic circuits decode instructions and set up the alu for the selected operation. most binary arithmetic is based on the addition algorithm, carrying out subtraction as negative addition. multiplication is not performed as a discrete operation but as a chain of addition and shift operations within the alu. the multiply instruction requires 11 internal clock cycles to complete this chain of operations. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc705c8a ? rev. 3 technical data motorola interrupts technical data ? mc68hc705c8a section 4. interrupts 4.1 contents 4.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 4.3 interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 4.3.1 software interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 4.3.2 external interrupt (irq ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 4.3.3 port b interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 4.3.4 capture/compare timer interrupts . . . . . . . . . . . . . . . . . . .55 4.3.5 sci interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 4.3.6 spi interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 4.4 interrupt processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 4.2 introduction this section describes how interrupts temporarily change the normal processing sequence. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data mc68hc705c8a ? rev. 3 50 interrupts interrupts 4.3 interrupt sources these sources can generate interrupts: software instructions (swi) external interrupt pin (irq ) port b pins serial communications interface (sci): ? sci transmit data register empty ? sci transmission complete ? sci receive data register full ? sci receiver overrun ? sci receiver input idle serial peripheral interface (spi): ? spi transmission complete ? spi mode fault ? spi overrun the irq pin, port b pins, sci, and spi can be masked (disabled) by setting the i bit of the condition code register (ccr). the software interrupt (swi) instruction is non-maskable. an interrupt temporarily changes the program sequence to process a particular event. an interrupt does not stop the execution of the instruction in progress but takes effect when the current instruction completes its execution. interrupt processing automatically saves the central processor unit (cpu) registers on the stack and loads the program counter with a user-defined vector address. 4.3.1 software interrupt the software interrupt instruction (swi) causes a non-maskable interrupt. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . interrupts interrupt sources mc68hc705c8a ? rev. 3 technical data motorola interrupts 4.3.2 external interrupt (irq ) an interrupt signal on the irq pin latches an external interrupt request. after completing the current instruction, the cpu tests these bits: irq latch i bit in the ccr setting the i bit in the ccr disables external interrupts. if the irq latch is set and the i bit is clear, the cpu then begins the interrupt sequence. the cpu clears the irq latch while it fetches the interrupt vector, so that another external interrupt request can be latched during the interrupt service routine. as soon as the i bit is cleared during the return-from-interrupt (rti) instruction, the cpu can recognize the new interrupt request. figure 4-1 shows the logic for external interrupts. figure 4-1 shows an external interrupt functional diagram. figure 4-2 shows an external interrupt timing diagram for the interrupt line. the timing diagram illustrates two treatments of the interrupt line to the processor. 1. two single pulses on the interrupt line are spaced far enough apart to be serviced. the minimum time between pulses is a function of the length of the interrupt service. once a pulse occurs, the next pulse normally should not occur until an rti occurs. this time (t ilil ) is obtained by adding 19 instruction cycles to the total number of cycles needed to complete the service routine (not including the rti instruction). 2. many interrupt lines are ? wire-ored ? to the irq line. if the interrupt line remains low after servicing an interrupt, then the cpu continues to recognize an interrupt. note: the internal interrupt latch is cleared in the first part of the interrupt service routine. therefore, a new external interrupt pulse could be latched and serviced as soon as the i bit is cleared. if the irq pin is not in use, connect it to the v dd pin. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data mc68hc705c8a ? rev. 3 52 interrupts interrupts figure 4-1. external interrupt internal function diagram figure 4-2. external interrupt timing r c dq q v dd external interrupt request i bit (ccr) internal reset (cop) external reset external interrupt being serviced (vector fetch) edge- and level-sensitive trigger option register interrupt pin irq latch por normally used with wired-or connection irq t ilih t ilil t ilih irq pin irq 1 irq n . . . a. edge-sensitive trigger condition. the minimum pulse width (t ilih ) is either 125 ns (f op = 2.1 mhz) or 250 ns (f op = 1 mhz). the period t ilil should not be less than the number of t cyc cycles it takes to execute the interrupt service routine plus 19 t cyc cycles. b. level-sensitive trigger condition. if the interrupt line remains low after servicing an interrupt, then the cpu continues to recognize an interrupt. (internal) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . interrupts interrupt sources mc68hc705c8a ? rev. 3 technical data motorola interrupts 4.3.3 port b interrupts when these three conditions are true, a port b pin (pbx) acts as an external interrupt pin: the corresponding port b pullup bit (pbpux) in mask option register 1 (mor1) is programmed to a logic 1. the corresponding port b data direction bit (ddrbx) in data direction register b (ddrb) is a logic 0. the clear interrupt mask (cli) instruction has cleared the i bit in the ccr. mor1 is an erasable, programmable read-only memory (eprom) register that enables the port b pullup device. data from mor1 is latched on the rising edge of the voltage on the reset pin. see 9.5.2 mask option register 1 . port b external interrupt pins can be falling-edge sensitive only or both falling-edge and low-level sensitive, depending on the state of the irq bit in the option register at location $1fdf. when the irq bit is a logic 1, a falling edge or a low level on a port b external interrupt pin latches an external interrupt request. as long as any port b external interrupt pin is low, an external interrupt request is present, and the cpu continues to execute the interrupt service routine. when the irq bit is a logic 0, a falling-edge only on a port b external interrupt pin latches an external interrupt request. a subsequent port b external interrupt request can be latched only after the voltage level of the previous port b external interrupt signal returns to a logic 1 and then falls again to a logic 0. figure 4-3 shows the port b input/output (i/o) logic. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data mc68hc705c8a ? rev. 3 54 interrupts interrupts figure 4-3. port b i/o logic pb7 external interrupt request data direction register b bit ddrb7 port b data register bit pb7 read $0005 write $0001 read $0001 reset internal data bus write $0005 pbpu7 from other v dd port b pins d c q r q i bit v dd from ccr reset external interrupt vector fetch irq irq from option register from mor1 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . interrupts interrupt sources mc68hc705c8a ? rev. 3 technical data motorola interrupts 4.3.4 capture/compare timer interrupts setting the i bit in the ccr disables all interrupts except for swi. 4.3.5 sci interrupts the serial communications interface (sci) can generate these interrupts: transmit data register empty interrupt transmission complete interrupt receive data register full interrupt receiver overrun interrupt receiver input idle interrupt setting the i bit in the ccr disables all sci interrupts. sci transmit data register empty interrupt ? the transmit data register empty bit (tdre) indicates that the sci data register is ready to receive a byte for transmission. tdre becomes set when data in the sci data register transfers to the transmit shift register. tdre generates an interrupt request if the transmit interrupt enable bit (tie) is set also. sci transmission complete interrupt ? the transmission complete bit (tc) indicates the completion of an sci transmission. tc becomes set when the tdre bit becomes set and no data, preamble, or break character is being transmitted. tc generates an interrupt request if the transmission complete interrupt enable bit (tcie) is set also. sci receive data register full interrupt ? the receive data register full bit (rdrf) indicates that a byte is ready to be read in the sci data register. rdrf becomes set when the data in the receive shift register transfers to the sci data register. rdrf generates an interrupt request if the receive interrupt enable bit (rie) is set also. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data mc68hc705c8a ? rev. 3 56 interrupts interrupts sci receiver overrun interrupt ? the overrun bit (or) indicates that a received byte is lost because software has not read the previously received byte. or becomes set when a byte shifts into the receive shift register before software reads the word already in the sci data register. or generates an interrupt request if the receive interrupt enable bit (rie) is set also. sci receiver input idle interrupt ? the receiver input idle bit (idle) indicates that the sci receiver input is not receiving data. idle becomes set when 10 or 11 consecutive logic 1s appear on the receiver input. idle generates an interrupt request if the idle line interrupt enable bit (ilie) is set also. 4.3.6 spi interrupts the serial peripheral interrupt (spi) can generate these interrupts: spi transmission complete interrupt spi mode fault interrupt setting the i bit in the ccr disables all spi interrupts. spi transmission complete interrupt ? the spi flag bit (spif) in the spi status register indicates the completion of an spi transmission. spif becomes set when a byte shifts into or out of the spi data register. spif generates an interrupt request if the spie bit is set also. spi mode fault interrupt ? the mode fault bit (modf) in the spi status register indicates an spi mode error. modf becomes set when a logic 0 occurs on the pd5/ss pin while the master bit (mstr) in the spi control register is set. modf generates an interrupt request if the spie bit is set also. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . interrupts interrupt processing mc68hc705c8a ? rev. 3 technical data motorola interrupts 4.4 interrupt processing the cpu takes these actions to begin servicing an interrupt: 1. stores the cpu registers on the stack in the order shown in figure 4-4 2. sets the i bit in the ccr to prevent further interrupts 3. loads the program counter with the contents of the appropriate interrupt vector locations as shown in table 4-1 . the return-from-interrupt (rti) instruction causes the cpu to recover the cpu registers from the stack as shown in figure 4-4 . table 4-1. reset/interrupt vector addresses function source local mask global mask priority (1 = highest) vector address reset power-on logic none none 1 $1ffe ? $1fff reset pin software interrupt (swi) user code none none same priority as any instruction $1ffc ? $1ffd external interrupt irq pin none i bit 2 $1ffa ? $1ffb port b pins timer interrupts icf bit icie bit i bit 3 $1ff8 ? $1ff9 ocf bit ocie bit tof bit toie bit sci interrupts tdre bit tcie bit i bit 4 $1ff6 ? $1ff7 tc bit rdrf bit rie bit or bit idle bit ilie bit spi interrupts spif bit spie i bit 5 $1ff4 ? $1ff5 modf bit f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data mc68hc705c8a ? rev. 3 58 interrupts interrupts figure 4-4. interrupt stacking order note: if more than one interrupt request is pending, the cpu fetches the vector of the higher priority interrupt first. a higher priority interrupt does not interrupt a lower priority interrupt service routine unless the lower priority interrupt service routine clears the i bit. see table 4-1 for a priority listing. figure 4-5 shows the sequence of events caused by an interrupt. condition code register $00c0 (bottom of stack) $00c1 $00c2 accumulator index register program counter (high byte) program counter (low byte) $00fd $00fe $00ff (top of stack) 1 2 3 4 5 5 4 3 2 1 unstacking order stacking order f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . interrupts interrupt processing mc68hc705c8a ? rev. 3 technical data motorola interrupts figure 4-5. reset and interrupt processing flowchart external i bit in from reset timer interrupt? fetch next instruction swi instruction? rti instruction? 1. stack pc, x, a, ccr 2. set i bit 3. load pc with vector yes yes yes yes yes restore registers from stack: execute instruction clear irq request latch no no no no no sci interrupt? yes yes no no ccr register spi interrupt? swi: irq : timer: sci: spi: $1ffc ? $1ffd $1ffa ? $1ffb $1ff8 ? $1ff9 $1ff6 ? $1ff7 $1ff4 ? $1ff5 set? irq interrupt? ccr, a, x, pc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data mc68hc705c8a ? rev. 3 60 interrupts interrupts f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc705c8a ? rev. 3 technical data motorola resets technical data ? mc68hc705c8a section 5. resets 5.1 contents 5.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 5.3 reset sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 5.3.1 power-on reset (por) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 5.3.2 external reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 5.3.3 programmable and non-programmable cop watchdog resets . . . . . . . . . . . . . . . . . . . . . . . . . . 62 5.3.3.1 programmable cop watchdog reset . . . . . . . . . . . . . . .63 5.3.3.2 non-programmable cop watchdog . . . . . . . . . . . . . . . .66 5.3.4 clock monitor reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 5.2 introduction this section describes how resets initialize the microcontroller unit (mcu). 5.3 reset sources a reset immediately stops the operation of the instruction being executed, initializes certain control bits, and loads the program counter with a user-defined reset vector address. these conditions produce a reset: power-on reset (por) ? initial power-up external reset ? a logic 0 applied to the reset pin internal programmable computer operating properly (cop) watchdog timer reset internal non-programmable cop watchdog timer reset internal clock monitor reset f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data mc68hc705c8a ? rev. 3 62 resets resets 5.3.1 power-on reset (por) a positive transition on the v dd pin generates a power-on reset (por). the por is strictly for the power-up condition and cannot be used to detect drops in power supply voltage. a 4064 t cyc (internal clock cycle) delay after the oscillator becomes active allows the clock generator to stabilize. if the reset pin is at logic 0 at the end of 4064 t cyc , the mcu remains in the reset condition until the signal on the reset pin goes to logic 1. 5.3.2 external reset the minimum time required for the mcu to recognize a reset is 1 1/2 t cyc . however, to guarantee that the mcu recognizes an external reset as an external reset and not as a cop or clock monitor reset, the reset pin must be low for eight t cyc . after six t cyc , the input on the reset pin is sampled. if the pin is still low, an external reset has occurred. if the input is high, then the mcu assumes that the reset was initiated internally by either the cop watchdog timer or by the clock monitor. this method of differentiating between external and internal reset conditions assumes that the reset pin will rise to a logic 1 less than two t cyc after its release and that an externally generated reset should stay active for at least eight t cyc . 5.3.3 programmable and non-programmable cop watchdog resets a timeout of a cop watchdog generates a cop reset. a cop watchdog, once enabled, is part of a software error detection system and must be cleared periodically to start a new timeout period. the mc68hc705c8a has two different cop watchdogs for compatibility with devices such as the mc68hc705c8 and the mc68hc05c4a: 1. programmable cop watchdog reset 2. non-programmable cop watchdog one cop has four programmable timeout periods and the other has a fixed non-programmable timeout period. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . resets reset sources mc68hc705c8a ? rev. 3 technical data motorola resets 5.3.3.1 programmable cop watchdog reset a timeout of the 18-stage ripple counter in the programmable cop watchdog generates a reset. figure 5-1 is a diagram of the programmable cop watchdog. two registers control and monitor operation of the programmable cop watchdog: cop reset register (coprst), $001d cop control register (copcr), $001e to clear the programmable cop watchdog and begin a new timeout period, write these values to the cop reset register (coprst). see figure 5-2 . 1. $55 2. $aa the $55 write must precede the $aa write. instructions may be executed between the write operations provided that the cop watchdog does not time out before the second write. figure 5-1. programmable cop watchdog diagram 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 4 4 2 2 2 2 2 2 2 21 2 19 2 17 2 13 2 15 cm1 cm0 coprst pcope reset internal clock (f op ) programmable cop watchdog (mc68hc705c8 type) 2 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data mc68hc705c8a ? rev. 3 64 resets resets the programmable cop control register (copcr) shown in figure 5-3 does these functions: flags programmable cop watchdog resets enables the clock monitor enables the programmable cop watchdog controls the timeout period of the programmable cop watchdog copf ? cop flag this read-only bit is set when a timeout of the programmable cop watchdog occurs or when the clock monitor detects a slow or absent internal clock. clear the copf bit by reading the cop control register. reset has no effect on the copf bit. 1 = cop timeout or internal clock failure 0 = no cop timeout and no internal clock failure address: $001d bit 7654321bit 0 read: write:bit 7654321bit 0 reset:uuuuuuuu = unimplemented u = unaffected figure 5-2. programmable cop reset register (coprst) address: $001e bit 7654321bit 0 read: 0 0 0 copf cme pcope cm1 cm0 write: reset:000u0000 = unimplemented u = unaffected figure 5-3. programmable cop control register (copcr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . resets reset sources mc68hc705c8a ? rev. 3 technical data motorola resets cme ? clock monitor enable bit this read/write bit enables the clock monitor. the clock monitor sets the copf bit and generates a reset if it detects an absent internal clock for a period of from 5 s to 100 s. cme is readable and writable at any time. reset clears the cme bit. 1 = clock monitor enabled 0 = clock monitor disabled note: do not enable the clock monitor in applications with an internal clock frequency of 200 khz or less. if the clock monitor detects a slow clock, it drives the bidirectional reset pin low for four clock cycles. if the clock monitor detects an absent clock, it drives the reset pin low until the clock recovers. pcope ? programmable cop enable bit this read/write bit enables the programmable cop watchdog. pcope is readable at any time but can be written only once after reset. reset clears the pcope bit. 1 = programmable cop watchdog enabled 0 = programmable cop watchdog disabled note: programming the non-programmable cop enable bit (ncope) in mask option register 2 (mor2) to logic 1 enables the non-programmable cop watchdog. setting the pcope bit while the ncope bit is programmed to logic 1 enables both cop watchdogs to operate at the same time. (see 9.5.3 mask option register 2 .) cm1 and cm0 ? cop mode bits these read/write bits select the timeout period of the programmable cop watchdog. (see table 5-1 .) cm1 and cm0 can be read anytime but can be written only once. they can be cleared only by reset. bits 7 ? 5 ? unused bits 7 ? 5 always read as logic 0s. reset clears bits 7 ? 5. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data mc68hc705c8a ? rev. 3 66 resets resets 5.3.3.2 non-programmable cop watchdog a timeout of the 18-stage ripple counter in the non-programmable cop watchdog generates a reset. the timeout period is 65.536 ms when f osc = 4 mhz. the timeout period for the non-programmable cop timer is a direct function of the crystal frequency. the equation is: two memory locations control operation of the non-programmable cop watchdog: 1. non-programmable cop enable bit (ncope) in mask option register 2 (mor2) programming the ncope bit in mor2 to a logic 1 enables the non-programmable cop watchdog. see 9.5.3 mask option register 2 . note: writing a logic 1 to the programmable cop enable bit (pcope) in the cop control register enables the programmable cop watchdog. setting the pcope bit while the ncope bit is programmed to logic 1 enables both cop watchdogs to operate at the same time. table 5-1. programmable cop timeout period selection cm1:cm0 cop timeout rate programmable cop timeout period f osc = 4.0 mhz f op = 2.0 mhz f osc = 3.5795 mhz f op = 1.7897 mhz f osc = 2.0 mhz f op = 1.0 mhz f osc = 1.0 mhz f op = 0.5 mhz 00 f op 2 15 16.38 ms 18.31 ms 32.77 ms 65.54 ms 01 f op 2 17 65.54 ms 73.24 ms 131.07 ms 262.14 ms 10 f op 2 19 262.14 ms 292.95 ms 524.29 ms 1.048 s 11 f op 2 21 1.048 s 1.172 s 2.097 s 4.194 s 262,144 f osc timeout period = f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . resets reset sources mc68hc705c8a ? rev. 3 technical data motorola resets 2. cop clear bit (copc) at address $1ff0 to clear the non-programmable cop watchdog and start a new cop timeout period, write a logic 0 to bit 0 of address $1ff0. reading address $1ff0 returns the mask option register 1 (mor1) data at that location. see 9.5.2 mask option register 1 . note: the non-programmable watchdog cop is disabled in bootloader mode, even if the ncope bit is programmed. figure 5-4 is a diagram of the non-programmable cop. figure 5-4. non-programmable cop watchdog diagram 5.3.4 clock monitor reset when the cme bit in the cop control register is set, the clock monitor detects the absence of the internal bus clock for a certain period of time. the timeout period depends on processing parameters and varies from 5 s to 100 s, which implies that systems using a bus clock rate of 200 khz or less should not use the clock monitor function. if a slow or absent clock is detected, the clock monitor causes a system reset. the reset is issued to the external system for four bus cycles using the bidirectional reset pin. special consideration is required when using the stop instruction with the clock monitor. since stop causes the system clocks to halt, the clock monitor issues a system reset when stop is executed. 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 ncope non-programmable cop watchdog (mc68hc05c4a type) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data mc68hc705c8a ? rev. 3 68 resets resets the clock monitor is a useful backup to the cop watchdog system. because the watchdog timer requires a clock to function, it cannot indicate a system clock failure. the clock monitor would detect such a condition and force the mcu to a reset state. clocks are not required for the mcu to reach a reset condition. they are, however, required to bring the mcu through the reset sequence and back to run condition. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc705c8a ? rev. 3 technical data motorola low-power modes technical data ? mc68hc705c8a section 6. low-power modes 6.1 contents 6.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 6.3 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 6.3.1 sci during stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 6.3.2 spi during stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 6.3.3 programmable cop watchdog in stop mode . . . . . . . . . . .71 6.3.4 non-programmable cop watchdog in stop mode . . . . . . .73 6.4 wait mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 6.4.1 programmable cop watchdog in wait mode . . . . . . . . . . .75 6.4.2 non-programmable cop watchdog in wait mode . . . . . . .75 6.5 data-retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 6.2 introduction this section describes the three low-power modes: stop mode wait mode data-retention mode 6.3 stop mode the stop instruction places the microcontroller unit (mcu) in its lowest power consumption mode. in stop mode, the internal oscillator is turned off, halting all internal processing including timer, serial communications interface (sci), and master mode serial peripheral interface (spi) operation. see figure 6-1 . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data mc68hc705c8a ? rev. 3 70 low-power modes low-power modes figure 6-1. stop/wait mode function flowchart during stop mode, the i bit in the condition code register (ccr) is cleared to enable external interrupts. all other registers and memory remain unaltered. all input/output (i/o) lines remain unchanged. the processor can be brought out of stop mode only by an external interrupt or reset. no yes yes yes yes yes no no no no yes no no yes stop reset external interrupt (irq ) turn on oscillator wait for time delay to stabilize 1. fetch reset vector 2. service interrupt: a. stack b. set i bit c. vector to interrupt routine stop oscillator and all clocks clear i bit wait oscillator active timer, sci, and spi clocks active cpu clocks stopped reset external interrupt (irq ) internal timer interrupt internal sci interrupt internal spi interrupt restart cpu clock 1. fetch reset vector 2. service interrupt: a. stack b. set i bit c. vector to interrupt routine clear i bit or or f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . low-power modes stop mode mc68hc705c8a ? rev. 3 technical data motorola low-power modes 6.3.1 sci during stop mode when the mcu enters stop mode, the baud rate generator stops, halting all sci activity. if the stop instruction is executed during a transmitter transfer, that transfer is halted. if a low input to the irq pin is used to exit stop mode, the transfer resumes. if the sci receiver is receiving data and stop mode is entered, received data sampling stops because the baud rate generator stops, and all subsequent data is lost. therefore, all sci transfers should be in the idle state when the stop instruction is executed. 6.3.2 spi during stop mode when the mcu enters stop mode, the baud rate generator stops, terminating all master mode spi operations. if the stop instruction is executed during an spi transfer, that transfer halts until the mcu exits stop mode by a low signal on the irq pin. if reset is used to exit stop mode, the spi control and status bits are cleared, and the spi is disabled. if the mcu is in slave mode when the stop instruction is executed, the slave spi continues to operate and can still accept data and clock information in addition to transmitting its own data back to a master device. at the end of a possible transmission with a slave spi in stop mode, no flags are set until a low on the irq pin wakes up the mcu. note: although a slave spi in stop mode can exchange data with a master spi, the status bits of a slave spi are inactive in stop mode. 6.3.3 programmable cop watchdog in stop mode the stop instruction turns off the internal oscillator and suspends the computer operating properly (cop) watchdog counter. if the reset pin brings the mcu out of stop mode, the reset function clears and disables the cop watchdog. if the irq pin brings the mcu out of stop mode, the cop counter resumes counting from its suspended value after the 4064-t cyc clock stabilization delay. see figure 6-2 . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data mc68hc705c8a ? rev. 3 72 low-power modes low-power modes note: if the clock monitor is enabled (cme = 1), the stop instruction causes the clock monitor to time out and reset the mcu. figure 6-2. programmable cop watchdog in stop mode (pcope = 1) flowchart stabilization stop external reset? no no turn on internal oscillator yes yes end of delay? yes no 1. load pc with reset vector or 2. service interrupt: a. save cpu registers on stack b. set i bit in ccr c. load pc with interrupt vector clear i bit in ccr turn off internal oscillator turn on internal clock suspend cop counter turn on internal oscillator end of stabilization delay? yes no 1. load pc with reset vector or 2. service interrupt: a. save cpu registers on stack b. set i bit in ccr c. load pc with interrupt vector turn on internal clock clear cop counter clear pcope bit in copcr resume cop watchdog count external interrupt? f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . low-power modes wait mode mc68hc705c8a ? rev. 3 technical data motorola low-power modes 6.3.4 non-programmable cop watchdog in stop mode the stop instruction has these effects on the non-programmable cop watchdog: turns off the oscillator and the cop watchdog counter clears the cop watchdog counter if the reset pin brings the mcu out of stop mode, the cop watchdog begins counting immediately. the reset function clears the cop counter again after the 4064-t cyc clock stabilization delay. if the irq pin brings the mcu out of stop mode, the cop watchdog begins counting immediately. the irq function does not clear the cop counter again after the 4064-t cyc clock stabilization delay. see figure 6-3 . note: if the clock monitor is enabled (cme = 1), the stop instruction causes it to time out and reset the mcu. 6.4 wait mode the wait instruction places the mcu in an intermediate power consumption mode. all central processor unit (cpu) activity is suspended, but the oscillator, capture/compare timer, sci, and spi remain active. any interrupt or reset brings the mcu out of wait mode. see figure 6-1 . the wait instruction has these effects on the cpu: clears the i bit in the condition code register, enabling interrupts stops the cpu clock, but allows the internal clock to drive the capture/compare timer, sci, and spi the wait instruction does not affect any other registers or i/o lines. the capture/compare timer, sci, and spi can be enabled to allow a periodic exit from wait mode. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data mc68hc705c8a ? rev. 3 74 low-power modes low-power modes figure 6-3. non-programmable cop watchdog in stop mode (ncope = 1) flowchart stabilization stop external reset? no no turn on internal oscillator yes yes end of delay? yes no 1. load pc with reset vector or 2. service interrupt: a. save cpu registers on stack b. set i bit in ccr c. load pc with interrupt vector clear i bit in ccr clear cop counter turn on internal clock turn off internal oscillator turn on internal oscillator end of stabilization delay? yes no 1. load pc with reset vector or 2. service interrupt: a. save cpu registers on stack b. set i bit in ccr c. load pc with interrupt vector clear cop counter turn on cop watchdog external interrupt? turn off cop counter turn on cop watchdog turn on internal clock f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . low-power modes data-retention mode mc68hc705c8a ? rev. 3 technical data motorola low-power modes 6.4.1 programmable cop watchdog in wait mode the programmable cop watchdog is active during wait mode. software must periodically bring the mcu out of wait mode to clear the programmable cop watchdog. 6.4.2 non-programmable cop watchdog in wait mode the non-programmable cop watchdog is active during wait mode. software must periodically bring the mcu out of wait mode to clear the non-programmable cop watchdog. 6.5 data-retention mode in data-retention mode, the mcu retains random-access memory (ram) contents and cpu register contents at v dd voltages as low as 2.0 vdc. the data-retention feature allows the mcu to remain in a low power-consumption state during which it retains data, but the cpu cannot execute instructions. to put the mcu in data-retention mode: 1. drive the reset pin to logic 0. 2. lower v dd voltage. the reset pin must remain low continuously during data-retention mode. to take the mcu out of data-retention mode: 1. return v dd to normal operating voltage. 2. return the reset pin to logic 1. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data mc68hc705c8a ? rev. 3 76 low-power modes low-power modes f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc705c8a ? rev. 3 technical data motorola parallel input/output (i/o) technical data ? mc68hc705c8a section 7. parallel input/output (i/o) 7.1 contents 7.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 7.3 port a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 7.3.1 port a data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 7.3.2 data direction register a. . . . . . . . . . . . . . . . . . . . . . . . . . . 79 7.3.3 port a logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 7.4 port b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 7.4.1 port b data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 7.4.2 data direction register b. . . . . . . . . . . . . . . . . . . . . . . . . . . 82 7.4.3 port b logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 7.5 port c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 7.5.1 port c data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 7.5.2 data direction register c. . . . . . . . . . . . . . . . . . . . . . . . . . . 86 7.5.3 port c logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 7.6 port d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 7.2 introduction this section describes the programming of ports a, b, c, and d. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data mc68hc705c8a ? rev. 3 78 parallel input/output (i/o) parallel input/output (i/o) 7.3 port a port a is an 8-bit, general-purpose, bidirectional input/output (i/o) port. 7.3.1 port a data register the port a data register (porta) shown in figure 7-1 contains a data latch for each of the eight port a pins. when a port a pin is programmed to be an output, the state of its data register bit determines the state of the output pin. when a port a pin is programmed to be an input, reading the port a data register returns the logic state of the pin. pa7 ? pa0 ? port a data bits these read/write bits are software programmable. data direction of each bit is under the control of the corresponding bit in data direction register a. reset has no effect on port a data. address: $0000 bit 7654321bit 0 read: pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 write: reset: unaffected by reset figure 7-1. port a data register (porta) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . parallel input/output (i/o) port a mc68hc705c8a ? rev. 3 technical data motorola parallel input/output (i/o) 7.3.2 data direction register a the contents of data direction register a (ddra) shown in figure 7-2 determine whether each port a pin is an input or an output. writing a logic 1 to a ddra bit enables the output buffer for the associated port a pin; a logic 0 disables the output buffer. a reset clears all ddra bits, configuring all port a pins as inputs. ddra7 ? ddra0 ? port a data direction bits these read/write bits control port a data direction. reset clears bits ddra7 ? ddra0. 1 = corresponding port a pin configured as output 0 = corresponding port a pin configured as input note: avoid glitches on port a pins by writing to the port a data register before changing ddra bits from logic 0 to logic 1. address: $0004 bit 7654321bit 0 read: ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 write: reset:00000000 figure 7-2. data direction register a (ddra) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data mc68hc705c8a ? rev. 3 80 parallel input/output (i/o) parallel input/output (i/o) 7.3.3 port a logic figure 7-3 is a diagram of the port a i/o logic. figure 7-3. port a i/o logic when a port a pin is programmed to be an output, the state of its data register bit determines the state of the output pin. when a port a pin is programmed to be an input, reading the port a data register returns the logic state of the pin. the data latch can always be written, regardless of the state of its ddra bit. table 7-1 summarizes the operation of the port a pins. note: to avoid excessive current draw, tie all unused input pins to v dd or v ss , or change i/o pins to outputs by writing to ddra in user code as early as possible. table 7-1. port a pin functions ddra bit i/o pin mode accesses to ddra accesses to porta read/write read write 0 input, hi-z (1) 1. hi-z = high impedance ddra7 ? ddra0 pin pa7 ? pa0 (2) 2. writing affects data register but does not affect input. 1 output ddra7 ? ddra0 pa7 ? pa0 pa7 ? pa0 data direction register a bit ddrax pax port a data register bit pax read $0004 write $0000 read $0000 reset internal data bus write $0004 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . parallel input/output (i/o) port b mc68hc705c8a ? rev. 3 technical data motorola parallel input/output (i/o) 7.4 port b port b is an 8-bit, general-purpose, bidirectional i/o port. port b pins can also be configured to function as external interrupts. the port b pullup devices are enabled in mask option register 1 (mor1). see 9.5.2 mask option register 1 and 4.3.3 port b interrupts . 7.4.1 port b data register the port b data register (portb) shown in figure 7-4 contains a data latch for each of the eight port b pins. pb7 ? pb0 ? port b data bits these read/write bits are software programmable. data direction of each bit is under the control of the corresponding bit in data direction register b. reset has no effect on port b data. address: $0001 bit 7654321bit 0 read: pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 write: reset: unaffected by reset figure 7-4. port b data register (portb) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data mc68hc705c8a ? rev. 3 82 parallel input/output (i/o) parallel input/output (i/o) 7.4.2 data direction register b the contents of data direction register b (ddrb) shown in figure 7-5 determine whether each port b pin is an input or an output. writing a logic 1 to a ddrb bit enables the output buffer for the associated port b pin; a logic 0 disables the output buffer. a reset clears all ddrb bits, configuring all port b pins as inputs. if the pullup devices are enabled by mask option, setting a ddrb bit to a logic 1 turns off the pullup device for that pin. ddrb7 ? ddrb0 ? port b data direction bits these read/write bits control port b data direction. reset clears bits ddrb7 ? ddrb0. 1 = corresponding port b pin configured as output 0 = corresponding port b pin configured as input note: avoid glitches on port b pins by writing to the port b data register before changing ddrb bits from logic 0 to logic 1. address: $0005 bit 7654321bit 0 read: ddrb7 ddrb6 ddrb5 ddrb4 ddrb3 ddrb2 ddrb1 ddrb0 write: reset:00000000 figure 7-5. data direction register b (ddrb) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . parallel input/output (i/o) port b mc68hc705c8a ? rev. 3 technical data motorola parallel input/output (i/o) 7.4.3 port b logic figure 7-6 shows the port b i/o logic. figure 7-6. port b i/o logic pb7 external interrupt request data direction register b bit ddrb7 port b data register bit pb7 read $0005 write $0001 read $0001 reset internal data bus write $0005 pbpu7 from other v dd port b pins d c q r q i bit v dd from ccr reset external interrupt vector fetch irq irq from option register irq latch from mor1 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data mc68hc705c8a ? rev. 3 84 parallel input/output (i/o) parallel input/output (i/o) when a port b pin is programmed as an output, reading the port bit reads the value of the data latch and not the voltage on the pin itself. when a port b pin is programmed as an input, reading the port bit reads the voltage level on the pin. the data latch can always be written, regardless of the state of its ddrb bit. note: to avoid excessive current draw, tie all unused input pins to v dd or v ss , or for i/o pins change to outputs by writing to ddrb in user code as early as possible. table 7-2. port b pin functions ddrb bit i/o pin mode accesses to ddrb accesses to portb read/write read write 0 input, hi-z (1) 1. hi-z = high impedance ddrb7 ? ddrb0 pin pb7 ? pb0 (2) 2. writing affects data register but does not affect input. 1 output ddrb7 ? ddrb0 pb7 ? pb0 pb7 ? pb0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . parallel input/output (i/o) port c mc68hc705c8a ? rev. 3 technical data motorola parallel input/output (i/o) 7.5 port c port c is an 8-bit, general-purpose, bidirectional i/o port. pc7 has a high current sink and source capability. 7.5.1 port c data register the port c data register (portc) shown in figure 7-7 contains a data latch for each of the eight port c pins. when a port c pin is programmed to be an output, the state of its data register bit determines the state of the output pin. when a port c pin is programmed to be an input, reading the port c data register returns the logic state of the pin. pc7 ? pc0 ? port c data bits these read/write bits are software programmable. data direction of each bit is under the control of the corresponding bit in data direction register c. pc7 has a high current sink and source capability. reset has no effect on port c data. address: $0002 bit 7654321bit 0 read: pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 write: reset: unaffected by reset figure 7-7. port c data register (portc) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data mc68hc705c8a ? rev. 3 86 parallel input/output (i/o) parallel input/output (i/o) 7.5.2 data direction register c the contents of data direction register c (ddrc) shown in figure 7-8 determine whether each port c pin is an input or an output. writing a logic 1 to a ddrc bit enables the output buffer for the associated port c pin; a logic 0 disables the output buffer. a reset clears all ddrc bits, configuring all port c pins as inputs. ddrc7 ? ddrc0 ? port c data direction bits these read/write bits control port c data direction. reset clears bits ddrc7 ? ddrc0. 1 = corresponding port c pin configured as output 0 = corresponding port c pin configured as input note: avoid glitches on port c pins by writing to the port c data register before changing ddrc bits from logic 0 to logic 1. address: $0006 bit 7654321bit 0 read: ddrc7 ddrc6 ddrc5 ddrc4 ddrc3 ddrc2 ddrc1 ddrc0 write: reset:00000000 figure 7-8. data direction register c (ddrc) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . parallel input/output (i/o) port c mc68hc705c8a ? rev. 3 technical data motorola parallel input/output (i/o) 7.5.3 port c logic figure 7-9 shows port c i/o logic. figure 7-9. port c i/o logic when a port c pin is programmed as an output, reading the port bit reads the value of the data latch and not the voltage on the pin. when a port c pin is programmed as an input, reading the port bit reads the voltage level on the pin. the data latch can always be written, regardless of the st a t e o f its ddrc b i t. ta b l e 7 - 3 su m m a r i z es the o per a t i on of the p o rt c pins. note: to avoid excessive current draw, tie all unused input pins to v dd or v ss or change i/o pins to outputs by writing to ddrc in user code as early as possible. table 7-3. port c pin functions ddrc bit i/o pin mode accesses to ddrc accesses to portc read/write read write 0 input, hi-z (1) 1. hi-z = high impedance ddrc7 ? ddrc0 pin pc7 ? pc0 (2) 2. writing affects data register but does not affect input. 1 output ddrc7 ? ddrc0 pc7 ? pc0 pc7 ? pc0 pcx data direction register c bit ddrcx port c data register bit pcx read $0006 write $0002 read $0002 reset internal data bus write $0006 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data mc68hc705c8a ? rev. 3 88 parallel input/output (i/o) parallel input/output (i/o) 7.6 port d port d is a 7-bit, special-purpose, input-only port that has no data register. reading address $0003 returns the logic states of the port d pins. port d shares pins pd5 ? pd2 with the serial peripheral interface module (spi). when the spi is enabled, pd5 ? pd2 read as logic 0s. when the spi is disabled, reading address $0003 returns the logic states of the pd5 ? pd2 pins. port d shares pins pd1 and pd0 with the sci module. when the sci is enabled, pd1 and pd0 read as logic 0s. when the sci is disabled, reading address $0003 returns the logic states of the pd1 and pd0 pins. address: $0003 bit 7654321bit 0 read: pd7 ss sck mosi miso tdo rdi write: reset: unaffected by reset = unimplemented figure 7-10. port d fixed input register (portd) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc705c8a ? rev. 3 technical data motorola capture/compare timer technical data ? mc68hc705c8a section 8. capture/compare timer 8.1 contents 8.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 8.3 timer operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 8.3.1 input capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 8.3.2 output compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 8.4 timer i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 8.4.1 timer control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 8.4.2 timer status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 8.4.3 timer registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 8.4.4 alternate timer registers. . . . . . . . . . . . . . . . . . . . . . . . . . . 98 8.4.5 input capture registers . . . . . . . . . . . . . . . . . . . . . . . . . . 100 8.4.6 output compare registers. . . . . . . . . . . . . . . . . . . . . . . . . 101 8.2 introduction this section describes the operation of the 16-bit capture/compare timer. figure 8-1 shows the structure of the timer module. figure 8-2 is a summary of the timer input/output (i/o) registers. 8.3 timer operation the core of the capture/compare timer is a 16-bit free-running counter. the counter is the timing reference for the input capture and output compare functions. the input capture and output compare functions can latch the times at which external events occur, measure input waveforms, and generate output waveforms and timing delays. software can read the value in the counter at any time without affecting the counter sequence. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data mc68hc705c8a ? rev. 3 90 capture/compare timer capture/compare timer figure 8-1. timer block diagram tcap edge select/ 16-bit comparator ocrh ($ 0016) ocrl ($0017) 16-bit counter atrh ($001a) atrl ($001b) tcmp detect logic pin control logic trh ($0018) trl ($0019) icrh ($0014) icrl ($0015) internal data bus timer control register timer status register timer interrupt request internal clock (xtal 2) tof ocf icf $0013 $0012 icie ocie toie iedg olvl overflow 4 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . capture/compare timer timer operation mc68hc705c8a ? rev. 3 technical data motorola capture/compare timer addr. register name bit 7 6 5 4 3 2 1 bit 0 $0012 timer control register (tcr) see page 94. read: icie ocie toie 0 0 0 iedg olvl write: reset: 0 0 0 0 0 0 u 0 $0013 timer status register (tsr) see page 96. read: icf ocf tof 0 0 0 0 0 write: reset: u u u 0 0 0 0 0 $0014 input capture register high (icrh) see page 100. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: unaffected by reset $0015 input capture register low (icrl) see page 100. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: unaffected by reset $0016 output compare register high (ocrh) see page 101. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: unaffected by reset $0017 output compare register low (ocrl) see page 101. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: unaffected by reset $0018 timer register high (trh) see page 97. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: reset initializes trh to $ff $0019 timer register low (trl) see page 97. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: reset initializes trl to $fc $001a alternate timer register high (atrh) see page 99. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: reset initializes atrh to $ff $001b alternate timer register low (atrl) see page 99. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: reset initializes atrl to $fc = unimplemented u = unaffected figure 8-2. timer i/o register summary f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data mc68hc705c8a ? rev. 3 92 capture/compare timer capture/compare timer because of the 16-bit timer architecture, the i/o registers for the input capture and output compare functions are pairs of 8-bit registers. because the counter is 16 bits long and preceded by a fixed divide-by-four prescaler, the counter rolls over every 262,144 internal clock cycles. timer resolution with a 4-mhz crystal is 2 s. 8.3.1 input capture the input capture function can record the time at which an external event occurs. when the input capture circuitry detects an active edge on the input capture pin (tcap), it latches the contents of the timer registers into the input capture registers. the polarity of the active edge is programmable. latching values into the input capture registers at successive edges of the same polarity measures the period of the input signal on the tcap pin. latching the counter values at successive edges of opposite polarity measures the pulse width of the signal. figure 8-3 shows the logic of the input capture function. figure 8-3. input capture operation tcap edge select/detect input capture register high input capture register low timer register high timer register low timer interrupt request logic 15 $0018 8 7 $0019 0 15 87 0 $0014 $0015 timer status register timer control register latch iedg $0012 $0013 icf ocf tof icie ocie toie olvl f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . capture/compare timer timer operation mc68hc705c8a ? rev. 3 technical data motorola capture/compare timer 8.3.2 output compare the output compare function can generate an output signal when the 16-bit counter reaches a selected value. software writes the selected value into the output compare registers. on every fourth internal clock cycle the output compare circuitry compares the value of the counter to the value written in the output compare registers. when a match occurs, the timer transfers the programmable output level bit (olvl) from the timer control register to the output compare pin (tcmp). software can use the output compare register to measure time periods, to generate timing delays, or to generate a pulse of specific duration or a pulse train of specific frequency and duty cycle on the tcmp pin. figure 8-4 shows the logic of the output compare function. figure 8-4. output compare operation 16-bit comparator output compare register high output compare register low counter high byte counter low byte pin control logic tcmp timer status register timer status register 15 0 15 8 7 0 timer interrupt request icie ocie toie icf ocf tof $0012 $0013 $0016 $0017 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data mc68hc705c8a ? rev. 3 94 capture/compare timer capture/compare timer 8.4 timer i/o registers these registers control and monitor the timer operation: timer control register (tcr) timer status register (tsr) timer registers (trh and trl) alternate timer registers (atrh and atrl) input capture registers (icrh and icrl) output compare registers (ocrh and ocrl) 8.4.1 timer control register the timer control register (tcr) as shown in figure 8-5 performs these functions: enables input capture interrupts enables output compare interrupts enables timer overflow interrupts controls the active edge polarity of the tcap signal controls the active level of the tcmp output address: $0012 bit 7654321bit 0 read: icie ocie toie 0 0 0 iedg olvl write: reset:000000u0 u = unaffected figure 8-5. timer control register (tcr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . capture/compare timer timer i/o registers mc68hc705c8a ? rev. 3 technical data motorola capture/compare timer icie ? input capture interrupt enable bit this read/write bit enables interrupts caused by an active signal on the tcap pin. reset clears the icie bit. 1 = input capture interrupts enabled 0 = input capture interrupts disabled ocie ? output compare interrupt enable bit this read/write bit enables interrupts caused by an active signal on the tcmp pin. reset clears the ocie bit. 1 = output compare interrupts enabled 0 = output compare interrupts disabled toie ? timer overflow interrupt enable bit this read/write bit enables interrupts caused by a timer overflow. reset clears the toie bit. 1 = timer overflow interrupts enabled 0 = timer overflow interrupts disabled iedg ? input edge bit the state of this read/write bit determines whether a positive or negative transition on the tcap pin triggers a transfer of the contents of the timer register to the input capture registers. reset has no effect on the iedg bit. 1 = positive edge (low-to-high transition) triggers input capture 0 = negative edge (high-to-low transition) triggers input capture olvl ? output level bit the state of this read/write bit determines whether a logic 1 or a logic 0 appears on the tcmp pin when a successful output compare occurs. reset clears the olvl bit. 1 = tcmp goes high on output compare 0 = tcmp goes low on output compare bits 4 ? 2 ? not used; these bits always read 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data mc68hc705c8a ? rev. 3 96 capture/compare timer capture/compare timer 8.4.2 timer status register the timer status register (tsr) is a read-only register shown in figure 8-6 contains flags for these events: an active signal on the tcap pin, transferring the contents of the timer registers to the input capture registers a match between the 16-bit counter and the output compare registers, transferring the olvl bit to the tcmp pin a timer rollover from $ffff to $0000 icf ? input capture flag the icf bit is set automatically when an edge of the selected polarity occurs on the tcap pin. clear the icf bit by reading the timer status register with icf set and then reading the low byte ($0015) of the input capture registers. reset has no effect on icf. 1 = input capture 0 = no input capture ocf ? output compare flag the ocf bit is set automatically when the value of the timer registers matches the contents of the output compare registers. clear the ocf bit by reading the timer status register with ocf set and then reading the low byte ($0017) of the output compare registers. reset has no effect on ocf. 1 = output compare 0 = no output compare address: $0013 bit 7654321bit 0 read: icf ocf tof 00000 write: reset:uuu00000 = unimplemented u = unaffected figure 8-6. timer status register (tsr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . capture/compare timer timer i/o registers mc68hc705c8a ? rev. 3 technical data motorola capture/compare timer tof ? timer overflow flag the tof bit is automatically set when the 16-bit counter rolls over from $ffff to $0000. clear the tof bit by reading the timer status register with tof set and then reading the low byte ($0019) of the timer registers. reset has no effect on tof. 1 = timer overflow 0 = no timer overflow bits 4 ? 0 ? not used; these bits always read 0 8.4.3 timer registers the read-only timer registers (trh and trl) shown in figure 8-7 contain the current high and low bytes of the 16-bit counter. reading trh before reading trl causes trl to be latched until trl is read. reading trl after reading the timer status register clears the timer overflow flag bit (tof). writing to the timer registers has no effect. bit 7654321bit 0 register name and address: timer register high ? $0018 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: reset initializes trh to $ff register name and address: timer register low ? $0019 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: reset initializes trl to $fc = unimplemented figure 8-7. timer registers (trh and trl) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data mc68hc705c8a ? rev. 3 98 capture/compare timer capture/compare timer reading trh returns the current value of the high byte of the counter and causes the low byte to be latched into a buffer, as shown in figure 8-8 . the buffer value remains fixed even if the high byte is read more than once. reading trl reads the transparent low byte buffer and completes the read sequence of the timer registers. figure 8-8. timer register reads note: to prevent interrupts from occurring between readings of trh and trl, set the interrupt mask (i bit) in the condition code register before reading trh, and clear the mask after reading trl. 8.4.4 alternate timer registers the alternate timer registers (atrh and atrl) shown in figure 8-9 contain the current high and low bytes of the 16-bit counter. reading atrh before reading atrl causes atrl to be latched until atrl is read. reading does not affect the timer overflow flag (tof). writing to the alternate timer registers has no effect. low byte buffer $0018 $0019 timer register high timer register low read trh latch internal data bus 15 7 0 0 7 8 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . capture/compare timer timer i/o registers mc68hc705c8a ? rev. 3 technical data motorola capture/compare timer reading atrh returns the current value of the high byte of the counter and causes the low byte to be latched into a buffer, as shown in figure 8-10 . figure 8-10. alternate timer register reads note: to prevent interrupts from occurring between readings of atrh and atrl, set the interrupt mask (i bit) in the condition code register before reading atrh, and clear the mask after reading atrl. bit 7654321bit 0 register name and address: alternate timer register high ? $001a read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: reset initializes atrh to $ff register name and address: alternate timer register low ? $001b read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: reset initializes atrl to $fc = unimplemented figure 8-9. alternate timer registers (atrh and atrl) low byte buffer $001a $001b read atrh latch internal data bus 15 7 0 0 7 8 alternate timer register high alternate timer register low f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data mc68hc705c8a ? rev. 3 100 capture/compare timer capture/compare timer 8.4.5 input capture registers when a selected edge occurs on the tcap pin, the current high and low bytes of the 16-bit counter are latched into the read-only input capture registers (icrh and icrl) shown in figure 8-11 . reading icrh before reading icrl inhibits further captures until icrl is read. reading icrl after reading the timer status register clears the input capture flag (icf). writing to the input capture registers has no effect. note: to prevent interrupts from occurring between readings of icrh and icrl, set the interrupt mask (i bit) in the condition code register before reading icrh and clear the mask after reading icrl. bit 7654321bit 0 register name and address: input capture register high ? $0014 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: unaffected by reset register name and address: input capture register low ? $0015 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: unaffected by reset = unimplemented figure 8-11. input capture registers (icrh and icrl) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . capture/compare timer timer i/o registers mc68hc705c8a ? rev. 3 technical data motorola capture/compare timer 8.4.6 output compare registers when the value of the 16-bit counter matches the value in the read/write output compare registers (ocrh and ocrl) shown in figure 8-12 , the planned tcmp pin action takes place. writing to ocrh before writing to ocrl inhibits timer compares until ocrl is written. reading or writing to ocrl after reading the timer status register clears the output compare flag (ocf). to prevent ocf from being set between the time it is read and the time the output compare registers are updated, use this procedure: 1. disable interrupts by setting the i bit in the condition code register. 2. write to ocrh. compares are now inhibited until ocrl is written. 3. clear bit ocf by reading the timer status register (tsr). 4. enable the output compare function by writing to ocrl. 5. enable interrupts by clearing the i bit in the condition code register. bit 7654321bit 0 register name and address: output compare register high ? $0016 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: unaffected by reset register name and address: output compare register low ? $0017 read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset: unaffected by reset figure 8-12. output compare registers (ocrh and ocrl) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data mc68hc705c8a ? rev. 3 102 capture/compare timer capture/compare timer f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc705c8a ? rev. 3 technical data motorola eprom/otprom (prom) technical data ? mc68hc705c8a section 9. eprom/otprom (prom) 9.1 contents 9.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 9.3 eprom/otprom (prom) programming . . . . . . . . . . . . . . .104 9.3.1 program register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 9.3.2 preprogramming steps . . . . . . . . . . . . . . . . . . . . . . . . . . .110 9.4 prom programming routines . . . . . . . . . . . . . . . . . . . . . . . . 111 9.4.1 program and verify prom. . . . . . . . . . . . . . . . . . . . . . . . .111 9.4.2 verify prom contents . . . . . . . . . . . . . . . . . . . . . . . . . . . .112 9.4.3 secure prom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 9.4.4 secure prom and verify . . . . . . . . . . . . . . . . . . . . . . . . . .113 9.4.5 secure prom and dump. . . . . . . . . . . . . . . . . . . . . . . . . .113 9.4.6 load program into ram and execute . . . . . . . . . . . . . . . .114 9.4.7 execute program in ram. . . . . . . . . . . . . . . . . . . . . . . . . . 115 9.4.8 dump prom contents. . . . . . . . . . . . . . . . . . . . . . . . . . . .115 9.5 control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 9.5.1 option register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 9.5.2 mask option register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 9.5.3 mask option register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 9.6 eprom erasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 9.2 introduction this section describes erasable, programmable read-only memory/one-time programmable read-only memory (eprom/otprom (prom)) programming. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data mc68hc705c8a ? rev. 3 104 eprom/otprom (prom) eprom/otprom (prom) 9.3 eprom/otprom (prom) programming the internal prom can be programmed efficiently using the motorola mc68hc05pgmr-2 programmer board, which can be purchased from a motorola-authorized distributor. the user can program the microcontroller unit (mcu) using this printed circuit board (pcb) in conjunction with an eprom device already programmed with user code. only standalone programming is discussed in this section. for more information concerning the mc68hc05pgmr and its usages, contact a local motorola representative for a copy of the mc68hc05pgmr programmer board user?s manual #2 , motorola document number mc68hc05pgmr2/d1. refer to figure 9-1 for an eprom programming flowchart. figure 9-2 provides a schematic of the mc68hc05pgmr pcb with the reference designators defined in table 9-1 . table 9-1. mc68hc05pgmr pcb reference designators reference designators device type ground +5 v +12 v ? 12 v v pp notes u1 2764 14, 20 1, 26, 27, 28 ?? ? 8 k x 8-bit eprom u2 mcu 20 40 ?? 3 40-pin dip socket u3 mcu 22 44 ?? 4 44-lead plcc socket u4 mc145406 9 16 1 8 ? driver/receiver vr1 nma0512s 2.5 1 6 4 ? dc-dc converter f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . eprom/otprom (prom) eprom/otprom (prom) programming mc68hc705c8a ? rev. 3 technical data motorola eprom/otprom (prom) figure 9-1. eprom/otprom programming flowchart yes no start apply v pp ntrys = 0 start at beginning of memory lat = 1 write prom data pgm = 1 wait 1 ms pgm = 0 lat = 0 write additional byte ntrys = ntrys + 1 ntrys = 2 v pp off end yes no f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data mc68hc705c8a ? rev. 3 106 eprom/otprom (prom) eprom/otprom (prom) figure 9-2. prom programming circuit 1. the asterisk (*) denotes option t 4 2 3 5 1 1 5 64 2 + 3 30 3 3 p3 1 8 29 2 2 16 9 14 15 5 6 8 20 1 7 1 26 28 20 25 22 24 21 23 2 +12 v off on s1 p1 +5 v +12 v ? 12 v v pp gnd rxd txd cts dsr dcd dtr gnd gnd u4 mc145406 +12 v ? 12 v +5 v on off vr1 nma0512s dc-dc converter (optional) v cc 0 v +v ? vgnd ? 12 v d1 1n4001 pd1 pd0 u1 2764 v pp +5 v nc v cc c5 0.1 f pgm ce (a10) (a11) (a12) a8 a9 a10 a11 oe gnd 14 d0 10 9 8 7 6 5 4 3 (a0) (a1) (a2) (a3) (a4) (a5) (a6) (a7) 11 12 13 15 16 17 18 19 r15 10 k pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 40 v dd v pp pd1 pd0 pa0 11 10 9 8 7 6 5 4 12 13 14 15 16 17 18 19 20 v ss pb1 pb0 pa7 pa6 pa5 pa4 pa3 pa2 u2 40-pin dip socket pa1 +5 v c1 100 f osc1 39 osc2 38 reset 1 irq 2 tcap 37 pd7 36 tcmp 35 pd5 34 pd4 33 pd2 32 31 pc5 pc6 pc0 pc1 pc2 pc3 pc4 23 22 28 27 26 25 24 (a8) (a9) (a10) (a11) (a12) pc7 21 m n l k j i h g f e d c b a (enable ) (a8) (a9) (d3) (d2) (d1) (d0) (d4) (d5) (d6) (d7) o p q r s pd3 pb2 pb3 pb4 pb5 pb6 pb7 a0 a1 a2 a3 a4 a5 a6 a7 27 d1 d2 d3 d4 d5 d6 d7 v pp a12 notes: 2. unless otherwise specified, resistors are in ohms, 3. device type numbers shown in circuit are for command only. 5% 1/4 w; capacitors are in f; voltages are dc. reference only. device type number varies with manufacturer. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . eprom/otprom (prom) eprom/otprom (prom) programming mc68hc705c8a ? rev. 3 technical data motorola eprom/otprom (prom) figure 9-2. prom programming circuit (continued) 1 2 3 12 a b c d e f g h i j k l +5 v r10* 470 ds2* m n verf (verf) (prog) prog ds1* r11* 470 +5 v o p q r s (d4) (d3) (d2) (d1) (d0) (a0) (a1) (a2) (a3) (a4) (a5) 17 15 16 14 13 12 11 10 9 8 7 pb4 pb3 pb2 pb1 pb0 pa0 pa1 pa2 pa3 pa4 pa5 c4 22 pf r5 10 m c3 22 pf 2.0 mhz y1 r13 10 k +5 v +5 v r3 10 k r9 10 k r8 10 k r7 10 k r6 10 k pa6 pa7 v pp nc irq reset v dd osc1 osc2 tcap nc pd7 tcmp pd5 pd4 pd3 pd2 pd1 pd0 pc0 pc1 pc2 u3 44-lead plcc socket c6 0.1 f nc pb5 pb6 pb7 v ss nc pc7 pc6 pc5 pc4 pc3 39 38 37 36 35 34 33 32 31 30 29 18 nc 19 20 21 22 23 24 25 (prog) 26 27 28 (verf) (d5) (d6) (d7) nc (a12) (a11) (a10) (a9) (a8) pd0 pd1 pd2 pd3 pd4 pd5 (a6) 6 (a7) 5 4 3 nc 2 1 44 43 42 41 40 nc +5 v pc7 pc6 pc5 pd0 pd1 pc4 pc3 pc2 pc1 pc0 pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 tcmp tcap 37 35 12 13 14 15 16 17 18 19 11 10 9 8 7 6 5 4 28 27 26 25 24 30 29 23 22 21 r12 10 k pd7 pd2 pd3 pd4 pd5 34 33 32 31 36 s6 s5 s4 s3 +5 v j2 +5 v irq reset 2 +5 v r4 10 k 40 39 38 3 1 p2 nc nc nc nc nc +12 v r2 10 k 2.7 k r1 nc out 1.0 f c2 s2 j1 20 v ss f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data mc68hc705c8a ? rev. 3 108 eprom/otprom (prom) eprom/otprom (prom) to program the prom mcu, the mcu is installed in the pcb, along with an eprom device programmed with user code; the mcu is then subjected to a series of routines. the routines necessary to program, verify, and secure the prom mcu are: program and verify prom verify prom contents only secure prom and verify secure prom and dump through the serial communications interface (sci) other board routines available to the user are: load program into random-access memory (ram) and execute execute program in ram dump prom contents (binary upload) the user first configures the mcu for the bootstrap mode of operations by installing a fabricated jumper across pins 1 and 2 of the board ? s mode select header, j1. next, the board ? s mode switches (s3, s4, s5, and s6) are set to determine the routine to be executed after the next reset, as shown in table 9-2 . table 9-2. prom programming routines routine s3s4s5s6 program and verify prom off off off off verify prom contents only off off on off secure prom contents and verify on off on off secure prom contents and dump on on on off load program into ram and execute off on off off execute program in ram off off off on dump prom contents off on on off f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . eprom/otprom (prom) eprom/otprom (prom) programming mc68hc705c8a ? rev. 3 technical data motorola eprom/otprom (prom) 9.3.1 program register the program register (prog) shown in figure 9-3 is used for prom programming. lat ? latch enable bit this bit is both readable and writable. 1 = enables prom data and address bus latches for programming on the next byte write cycle 0 = latch disabled. prom data and address buses are unlatched for normal cpu operations. pgm ? program bit if lat is cleared, pgm cannot be set. 1 = enables v pp power to the prom for programming 0 = v pp is disabled. bits 1 and 3 ? 7 ? not used; always read 0 address: $001c bit 7654321bit 0 read: 00000lat0pgm write: reset:00000000 figure 9-3. program register (prog) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data mc68hc705c8a ? rev. 3 110 eprom/otprom (prom) eprom/otprom (prom) 9.3.2 preprogramming steps before programming the prom using an mc68hc05pgmr pcb in standalone mode, the user should ensure that: a jumper is installed on pins 1 and 2 of mode select header j1. an eprom is programmed with the necessary user code. the erasure window (if any) of the device to be programmed is covered. v dd of +5 vdc is available on the board. v pp is available on the board. note: if the v pp level at the mcu exceeds +16 vdc, then the mc68hc705c8a mcu device will suffer permanent damage. once those conditions are met, the user should take these steps before beginning programming: 1. remove the v pp power source. 2. set switch 1 in the off position (removes v dd ). 3. place the programmed eprom in socket u1. 4. insert the erased prom mcu device to be programmed in the proper socket: ? mc68hc705c8s or mc68hc705c8p in socket u2 (40-pin dual in-line package (dip)) or ? mc68hc705c8fn in socket u3 (44-pin plastic leaded chip carrier (plcc)) with the device notch at the upper right corner of the socket. 5. set switch s2 in the reset position. note: no prom mcu should be inserted in or removed from its board socket (u2 or u3) while v pp (p1, slot 5) or v dd (switch 1) is active on the board. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . eprom/otprom (prom) prom programming routines mc68hc705c8a ? rev. 3 technical data motorola eprom/otprom (prom) 9.4 prom programming routines this subsection describes the routines necessary to program, verify, and secure the prom device, and other routines available to the user. 9.4.1 program and verify prom the program and verify prom routine copies the contents of the external eprom into the mcu prom with direct correspondence between the addresses. memory addresses in the mcu that are not implemented in prom are skipped. unprogrammed addresses in the eprom being copied should contain $00 bytes to speed up the programming process. to run the program and verify the prom routine on the prom mcu, take these steps: 1. set switch 1 in the on position (restores v dd ). 2. restore the v pp power source. 3. set switches s3, s4, s5, and s6 in the off position (selects proper routine). 4. set switch 2 in the out position (routine is activated). the red light-emitting diode (led) is illuminated, showing that the programming part of the routine is running. the led goes out when programming is finished. the verification part of the routine now begins. when the green led is illuminated, verification is successfully completed and the routine is finished. 5. set switch 2 in the reset position. at this point, if no other mcu is to be programmed or secured, remove v pp power from the board. if another routine is to be performed on the mcu being programmed, the user can then set switches s3, s4, s5, and s6 to the positions necessary to select the next routine, and begin the routine by setting switch 2 to the out position. if no other routine is to be performed, remove v dd from the board and remove the mcu from the programming socket. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data mc68hc705c8a ? rev. 3 112 eprom/otprom (prom) eprom/otprom (prom) 9.4.2 verify prom contents the verify prom contents routine is normally run automatically after the prom is programmed. direct entry to this routine causes the prom contents of the mcu to be compared to the contents of the external memory locations of the eprom at the same addresses. to invoke the verify prom contents routine of the mcu, take these steps: 1. set switch 1 in the on position (restores v dd ). 2. connect v pp to v dd . 3. set switches s3, s4, and s6 in the off position. 4. set s5 in the on position. 5. set switch 2 in the out position (routine is activated). the red led is not illuminated during this routine, since no programming takes place. if verification fails, the routine halts with the failing address in the external memory bus. when the green led is illuminated, verification is completed successfully and the routine is finished. 6. set switch 2 in the reset position. at this point, if another routine is to be performed on the mcu being programmed, the user can set switches s3, s4, s5, and s6 to the positions necessary to select the next routine and move switch s2 to the out position to start the routine. if no other routine is to be performed, remove v dd from the board and remove the mcu from the programming socket. 9.4.3 secure prom the secure prom routines are used after the prom is successfully programmed and verified. only the sec bit of the option register ($1fdf) is programmed, but v pp is necessary. once this bit is programmed, prom is secure and can be neither verified nor dumped. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . eprom/otprom (prom) prom programming routines mc68hc705c8a ? rev. 3 technical data motorola eprom/otprom (prom) 9.4.4 secure prom and verify this routine is used after the prom is programmed successfully to verify the contents of the mcu prom against the contents of the eprom and then to secure the prom. to accomplish this routine, take these steps: 1. set switch 1 in the on position (restores v dd ). 2. restore v pp power to the programming board. 3. set switches s4 and s6 in the off position. 4. set switches s3 and s5 in the on position. 5. set switch 2 in the out position (routine is activated). execution time for this routine is about one second. 6. set switch 2 in the reset position when the routine is completed. no led is illuminated during this routine. further, the end of the routine does not mean that the sec bit was verified. to ensure that security is properly enabled, attempt to perform another verify routine. if the green led does not light, the prom has been secured properly. 9.4.5 secure prom and dump this routine is used after the prom is successfully programmed to dump the contents of the mcu prom through the sci (binary upload) and then to secure the prom. to accomplish this routine, take these steps: 1. set switch 1 in the on position (restores v dd ). 2. restore v pp power to the programming board. 3. set switch s6 in the off position. 4. set switches s3, s4, and s5 in the on position. 5. set switch 2 in the out position (routine is activated). execution time for this routine is about one second. 6. set switch 2 in the reset position when the routine is completed. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data mc68hc705c8a ? rev. 3 114 eprom/otprom (prom) eprom/otprom (prom) no led is illuminated during this routine. further, the end of the routine does not mean that the sec bit was verified. to ensure that security is properly enabled, attempt to perform another verify routine. if the green led does not light, the prom has been secured properly. 9.4.6 load program into ram and execute in the load program in ram and execute routine, user programs are loaded via the sci port and then executed. data is loaded sequentially starting at address $0050. after the last byte is loaded, control is transferred to the ram program starting at $0051. the first byte loaded is the count of the total number of bytes in the program plus the count byte. the program starts at location $0051 in ram. during initialization, the sci is configured for eight data bits and one stop bit. the baud rate is 4800 with a 2-mhz crystal or 9600 with a 4-mhz crystal. to load a program into ram and execute it, take these steps: 1. set switch 1 in the on position (restores v dd ). 2. connect v pp to v dd . 3. set switches s3, s5, and s6 in the off position. 4. set switch s4 in the on position. 5. set switch 2 in the out position (routine is activated). the downloaded program starts executing as soon as the last byte is received by the sci. execution of the routine can be held off by setting the byte count in the count byte (the first byte loaded) to a value greater than the number of bytes to be loaded. after loading the last byte, the firmware waits for more data. program execution does not begin. at this point, placing switch 2 in the reset position resets the mcu with the ram data intact. any other routine can be entered, including the one to execute the program in ram, simply by setting switches s3 ? s6 as necessary to select the desired routine, then setting switch 2 in the out position. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . eprom/otprom (prom) prom programming routines mc68hc705c8a ? rev. 3 technical data motorola eprom/otprom (prom) 9.4.7 execute program in ram this routine allows the mcu to transfer control to a program previously loaded in ram. this program is executed once bootstrap mode is entered, if switch s6 is in the on position and switch 2 is in the out position, without any firmware initialization. the program must start at location $0051 to be compatible with the load program in ram routine. to run the execute program in ram routine, take these steps: 1. set switch 1 in the on position (restores v dd ). 2. connect v pp to v dd . 3. set switch s6 in the off position. 4. switches s3, s4, and s5 can be in either position. 5. set switch 2 in the out position (routine is activated). note: the non-programmable watchdog cop is disabled in bootloader mode, even if the ncope bit is programmed. 9.4.8 dump prom contents in the dump prom contents routine, the prom contents are dumped sequentially to the sci output, provided the prom has not been secured. the first location sent is $0020 and the last location sent is $1fff. unused locations are skipped so that no gaps exist in the data stream. the external memory address lines indicate the current location being sent. data is sent with eight data bits and one stop bit at 4800 baud with a 2-mhz crystal or 9600 baud with a 4-mhz crystal. to run the dump prom contents routine, take these steps: 1. set switch 1 in the on position (restores v dd ). 2. connect v pp to v dd . 3. set switches s3 and s6 in the off position. 4. set switches s4 and s5 in the on position. 5. set switch 2 in the out position (routine is activated). 6. once prom dumping is complete, set switch 2 in the reset position. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data mc68hc705c8a ? rev. 3 116 eprom/otprom (prom) eprom/otprom (prom) 9.5 control registers this subsection describes the three registers that control memory configuration, prom security, and irq edge or level sensitivity; port b pullups; and non-programmable cop enable/disable. 9.5.1 option register the option register shown in figure 9-4 is used to select the irq sensitivity, enable the prom security, and select the memory configuration. ram0 ? random-access memory control bit 0 1 = maps 32 bytes of ram into page zero starting at address $0030. addresses from $0020 to $002f are reserved. this bit can be read or written at any time, allowing memory configuration to be changed during program execution. 0 = provides 48 bytes of prom at location $0020 ? $005f. ram1 ? random-access memory control bit 1 1 = maps 96 bytes of ram into page one starting at address $0100. this bit can be read or written at any time, allowing memory configuration to be changed during program execution. 0 = provides 96 bytes of prom at location $0100. address: $1fdf bit 7654321bit 0 read: ram0 ram1 0 0 sec * irq 0 write: reset:0000 * u10 * implemented as an eprom cell = unimplemented u = unaffected figure 9-4. option register (option) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . eprom/otprom (prom) control registers mc68hc705c8a ? rev. 3 technical data motorola eprom/otprom (prom) sec ? security bit this bit is implemented as an eprom cell and is not affected by reset. 1 = security enabled 0 = security off; bootloader able to be enabled irq ? interrupt request pin sensitivity bit irq is set only by reset, but can be cleared by software. this bit can only be written once. 1 = irq pin is both negative edge- and level-sensitive. 0 = irq pin is negative edge-sensitive only. bits 5, 4, and 0 ? not used; always read 0 bit 2 ? unaffected by reset; reads either 1 or 0 9.5.2 mask option register 1 mask option register 1 (mor1) shown in figure 9-5 is an eprom register that enables the port b pullup devices. data from mor1 is latched on the rising edge of the voltage on the reset pin. see 4.3.3 port b interrupts . pbpu7 ? pbpu0/copc ? port b pullup enable bits 7 ? 0 these eprom bits enable the port b pullup devices. 1 = port b pullups enabled 0 = port b pullups disabled address: $1ff0 bit 7654321bit 0 read: pbpu7 pbpu6 pbpu5 pbpu4 pbpu3 pbpu2 pbpu1 pbpu0/ copc write: reset: unaffected by reset erased:00000000 figure 9-5. mask option register 1 (mor1) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data mc68hc705c8a ? rev. 3 118 eprom/otprom (prom) eprom/otprom (prom) note: pbpu0/copc programmed to a 1 enables the port b pullup bit. this bit is also used to clear the non-programmable cop (mc68hc05c4a type). writing to this bit to clear the cop will not affect the state of the port b pull-up (bit 0). see 5.3.3 programmable and non-programmable cop watchdog resets . when using the mc68hc705c8a in an mc68hc705c8 or mc68hsc705c8 application, program locations $1ff0 and $1ff1 to $00. 9.5.3 mask option register 2 mask option register 2 (mor2) shown in figure 9-6 is an eprom register that enables the non-programmable cop watchdog. data from mor2 is latched on the rising edge of the voltage on the reset pin. see 5.3.3 programmable and non-programmable cop watchdog resets . ncope ? non-programmable cop watchdog enable bit this eprom bit enables the non-programmable cop watchdog. 1 = non-programmable cop watchdog enabled 0 = non-programmable cop watchdog disabled address: $1ff1 bit 7654321bit 0 read: ncope write: reset: unaffected by reset erased:00000000 = unimplemented figure 9-6. mask option register 2 (mor2) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . eprom/otprom (prom) eprom erasing mc68hc705c8a ? rev. 3 technical data motorola eprom/otprom (prom) 9.6 eprom erasing the erased state of an eprom or otprom byte is $00. eprom devices can be erased by exposure to a high intensity ultraviolet (uv) light with a wave length of 2537 ? . the recommended erasure dosage (uv intensity on a given surface area x exposure time) is 15 ws/cm 2 . uv lamps should be used without short-wave filters, and the eprom device should be positioned about one inch from the uv source. otprom devices are shipped in an erased state. once programmed, they cannot be erased. electrical erasing procedures cannot be performed on either eprom or otprom devices. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data mc68hc705c8a ? rev. 3 120 eprom/otprom (prom) eprom/otprom (prom) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc705c8a ? rev. 3 technical data motorola serial communications interface (sci) technical data ? mc68hc705c8a section 10. serial communications interface (sci) 10.1 contents 10.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 10.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 10.4 sci data format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 10.5 sci operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123 10.5.1 transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123 10.5.2 receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 10.6 sci i/o registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 10.6.1 sci data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 10.6.2 sci control register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . .130 10.6.3 sci control register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . .131 10.6.4 sci status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 10.6.5 baud rate register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 10.2 introduction the serial communications interface (sci) module allows high-speed asynchronous communication with peripheral devices and other microcontroller units (mcus). f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data mc68hc705c8a ? rev. 3 122 serial communications interface (sci) serial communications interface (sci) 10.3 features features of the sci module include: standard mark/space non-return-to-zero format full-duplex operation 32 programmable baud rates programmable 8-bit or 9-bit character length separately enabled transmitter and receiver two receiver wakeup methods: ? idle line wakeup ? address mark wakeup interrupt-driven operation capability with five interrupt flags: ? transmitter data register empty ? transmission complete ? receiver data register full ? receiver overrun ? idle receiver input receiver framing error detection 1/16 bit-time noise detection 10.4 sci data format the sci uses the standard non-return-to-zero mark/space data format illustrated in figure 10-1 . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface (sci) sci operation mc68hc705c8a ? rev. 3 technical data motorola serial communications interface (sci) figure 10-1. sci data format 10.5 sci operation the sci allows full-duplex, asynchronous, rs232 or rs422 serial communication between the mcu and remote devices, including other mcus. the transmitter and receiver of the sci operate independently, although they use the same baud-rate generator. this subsection describes the operation of the sci transmitter and receiver. 10.5.1 transmitter figure 10-2 shows the structure of the sci transmitter. figure 10-3 is a summary of the sci transmitter input/output (i/o) registers. character length ? the transmitter can accommodate either 8-bit or 9-bit data. the state of the m bit in sci control register 1 (sccr1) determines character length. when transmitting 9-bit data, bit t8 in sccr1 is the ninth bit (bit 8). character transmission ? during transmission, the transmit shift register shifts a character out to the pd1/tdo pin. the sci data register (scdr) is the write-only buffer between the internal data bus and the transmit shift register. 8-bit data format (bit m in sccr1 clear) 9-bit data format (bit m in sccr1 set) start bit bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 stop bit next start bit bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 start bit stop bit next start bit f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data mc68hc705c8a ? rev. 3 124 serial communications interface (sci) serial communications interface (sci) figure 10-2. sci transmitter scdr ($0011) transmit shift register 7 6 5 4 3 2 1 0 8 h l transmitter control logic load from scdr shift enable preamble (all logic 1s) break (all logic 0s) pin buffer and control pd1/ tdo sci receive requests sci interrupt request 1x baud rate clock sccr1 ( $000e) sccr2 ($000f) scsr ($0010) tie tcie rie ilie te re rwu sbk tdre tc rdrf idle or nf fe r8 t8 m wake tie tdre tc tcie internal data bus f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface (sci) sci operation mc68hc705c8a ? rev. 3 technical data motorola serial communications interface (sci) writing a logic 1 to the te bit in sci control register 2 (sccr2) and then writing data to the scdr begins the transmission. at the start of a transmission, transmitter control logic automatically loads the transmit shift register with a preamble of logic 1s. after the preamble shifts out, the control logic transfers the scdr data into the shift register. a logic 0 start bit automatically goes into the least significant bit (lsb) position of the shift register, and a logic 1 stop bit goes into the most significant bit (msb) position. when the data in the scdr transfers to the transmit shift register, the transmit data register empty (tdre) flag in the sci status register (scsr) becomes set. the tdre flag indicates that the scdr can accept new data from the internal data bus. when the shift register is not transmitting a character, the pd1/tdo pin goes to the idle condition, logic 1. if software clears the te bit during the idle condition, and while tdre is set, the transmitter relinquishes control of the pd1/tdo pin. addr. register name bit 7 6 5 4 3 2 1 bit 0 $000d baud rate register (baud) see page 136. read: scp1 scp0 scr2 scr1 scr0 write: reset: u u 0 0 u u u u $000e sci control register 1 (sccr1) see page 130. read: r8 t8 m wake write: reset: u u u u $000f sci control register 2 (sccr2) see page 131. read: tie tcie rie ilie te re rwu sbk write: reset: 0 0 0 0 0 0 0 0 $0010 sci status register (scsr) see page 133. read: tdre tc rdrf idle or nf fe write: reset: 1 1 0 0 0 0 0 u $0011 sci data register (scdr) see page 129. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: unaffected by reset = unimplemented u = unaffected figure 10-3. sci transmitter i/o register summary f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data mc68hc705c8a ? rev. 3 126 serial communications interface (sci) serial communications interface (sci) break characters ? writing a logic 1 to the sbk bit in sccr2 loads the shift register with a break character. a break character contains all logic 0s and has no start and stop bits. break character length depends on the m bit in sccr1. as long as sbk is at logic 1, transmitter logic continuously loads break characters into the shift register. after software clears the sbk bit, the shift register finishes transmitting the last break character and then transmits at least one logic 1. the automatic logic 1 at the end of a break character is to guarantee the recognition of the start bit of the next character. idle characters ? an idle character contains all logic 1s and has no start or stop bits. idle character length depends on the m bit in sccr1. the preamble is a synchronizing idle character that begins every transmission. clearing the te bit during a transmission relinquishes the pd1/tdo pin after the last character to be transmitted is shifted out. the last character may already be in the shift register, or waiting in the scdr, or it may be a break character generated by writing to the sbk bit. toggling te from logic 0 to logic 1 while the last character is in transmission generates an idle character (a preamble) that allows the receiver to maintain control of the pd1/tdo pin. transmitter interrupts ? these sources can generate sci transmitter interrupt requests: ? transmit data register empty (tdre) ? the tdre bit in the scsr indicates that the scdr has transferred a character to the transmit shift register. tdre is a source of sci interrupt requests. the transmission complete interrupt enable bit (tcie) in sccr2 is the local mask for tdre interrupts. ? transmission complete (tc) ? the tc bit in the scsr indicates that both the transmit shift register and the scdr are empty and that no break or idle character has been generated. tc is a source of sci interrupt requests. the transmission complete interrupt enable bit (tcie) in sccr2 is the local mask for tc interrupts. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface (sci) sci operation mc68hc705c8a ? rev. 3 technical data motorola serial communications interface (sci) 10.5.2 receiver figure 10-4 shows the structure of the sci receiver. refer to figure 10-3 for a summary of the sci receiver i/o registers. figure 10-4. sci receiver receive shift register 7 6 5 4 3 2 1 0 8 pin buffer and control pd0/ rdi 16x baud rate clock data recovery stop start 16 idle wakeup logic scsr ($0010) tdre tc rdrf idle or nf fe scdr ($0011) sccr1 ($000e) r8 t8 m wake sccr2 ($000f) tie tcie rie ilie te re rwu sbk msb rdrf or rdrf rie idle ilie or rie sci transmit requests sci interrupt request internal data bus re m disable driver internal data bus f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data mc68hc705c8a ? rev. 3 128 serial communications interface (sci) serial communications interface (sci) character length ? the receiver can accommodate either 8-bit or 9-bit data. the state of the m bit in sci control register 1 (sccr1) determines character length. when receiving 9-bit data, bit r8 in sccr1 is the ninth bit (bit 8). character reception ? during reception, the receive shift register shifts characters in from the pd0/rdi pin. the sci data register (scdr) is the read-only buffer between the internal data bus and the receive shift register. after a complete character shifts into the receive shift register, the data portion of the character is transferred to the scdr, setting the receive data register full (rdrf) flag. the rdrf flag can be used to generate an interrupt. receiver wakeup ? so that the mcu can ignore transmissions intended only for other receivers in multiple-receiver systems, the mcu can be put into a standby state. setting the receiver wakeup enable (rwu) bit in sci control register 2 (sccr2) puts the mcu into a standby state during which receiver interrupts are disabled. either of two conditions on the pd0/rdi pin can bring the mcu out of the standby state: ? idle input line condition ? if the pd0/rdi pin is at logic 1 long enough for 10 or 11 logic 1s to shift into the receive shift register, receiver interrupts are again enabled. ? address mark ? if a logic 1 occurs in the most significant bit position of a received character, receiver interrupts are again enabled. the state of the wake bit in sccr1 determines which of the two conditions wakes up the mcu. receiver noise immunity ? the data recovery logic samples each bit 16 times to identify and verify the start bit and to detect noise. any conflict between noise detection samples sets the noise flag (nf) in the scsr. the nf bit is set at the same time that the rdrf bit is set. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface (sci) sci i/o registers mc68hc705c8a ? rev. 3 technical data motorola serial communications interface (sci) framing errors ? if the data recovery logic does not detect a logic 1 where the stop bit should be in an incoming character, it sets the framing error (fe) bit in the scsr. the fe bit is set at the same time that the rdrf bit is set. receiver interrupts ? these sources can generate sci receiver interrupt requests: ? receive data register full (rdrf) ? the rdrf bit in the scsr indicates that the receive shift register has transferred a character to the scdr. ? receiver overrun (or) ? the or bit in the scsr indicates that the receive shift register shifted in a new character before the previous character was read from the scdr. ? idle input (idle) ? the idle bit in the scsr indicates that 10 or 11 consecutive logic 1s shifted in from the pd0/rdi pin. 10.6 sci i/o registers these i/o registers control and monitor sci operation: sci data register (scdr) sci control register 1 (sccr1) sci control register 2 (sccr2) sci status register (scsr) 10.6.1 sci data register the sci data register (scdr) shown in figure 10-5 is the buffer for characters received and for characters transmitted. address: $0011 bit 7654321bit 0 read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset: unaffected by reset figure 10-5. sci data register (scdr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data mc68hc705c8a ? rev. 3 130 serial communications interface (sci) serial communications interface (sci) 10.6.2 sci control register 1 sci control register 1 (sccr1) shown in figure 10-6 has these functions: stores ninth sci data bit received and ninth sci data bit transmitted controls sci character length controls sci wakeup method r8 ? bit 8 (received) when the sci is receiving 9-bit characters, r8 is the ninth bit of the received character. r8 receives the ninth bit at the same time that the scdr receives the other eight bits. reset has no effect on the r8 bit. t8 ? bit 8 (transmitted) when the sci is transmitting 9-bit characters, t8 is the ninth bit of the transmitted character. t8 is loaded into the transmit shift register at the same time that scdr is loaded into the transmit shift register. reset has no effect on the t8 bit. m ? character length bit this read/write bit determines whether sci characters are eight or nine bits long. the ninth bit can be used as an extra stop bit, as a receiver wakeup signal, or as a mark or space parity bit. reset has no effect on the m bit. 1 = 9-bit sci characters 0 = 8-bit sci characters address: $000e bit 7654321bit 0 read: r8 t8 mwake write: reset:uu uu = unimplemented u = unaffected figure 10-6. sci control register 1 (sccr1) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface (sci) sci i/o registers mc68hc705c8a ? rev. 3 technical data motorola serial communications interface (sci) wake ? wakeup bit this read/write bit determines which condition wakes up the sci: a logic 1 (address mark) in the most significant bit position of a received character or an idle condition of the pd0/rdi pin. reset has no effect on the wake bit. 1 = address mark wakeup 0 = idle line wakeup 10.6.3 sci control register 2 sci control register 2 (sccr2) shown in figure 10-7 has these functions: enables the sci receiver and sci receiver interrupts enables the sci transmitter and sci transmitter interrupts enables sci receiver idle interrupts enables sci transmission complete interrupts enables sci wakeup transmits sci break characters tie ? transmit interrupt enable bit this read/write bit enables sci interrupt requests when the tdre bit becomes set. reset clears the tie bit. 1 = tdre interrupt requests enabled 0 = tdre interrupt requests disabled address: $000f bit 7654321bit 0 read: tie tcie rie ilie te re rwu sbk write: reset:00000000 figure 10-7. sci control register 2 (sccr2) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data mc68hc705c8a ? rev. 3 132 serial communications interface (sci) serial communications interface (sci) tcie ? transmission complete interrupt enable bit this read/write bit enables sci interrupt requests when the tc bit becomes set. reset clears the tcie bit. 1 = tc interrupt requests enabled 0 = tc interrupt requests disabled rie ? receive interrupt enable bit this read/write bit enables sci interrupt requests when the rdrf bit or the or bit becomes set. reset clears the rie bit. 1 = rdrf interrupt requests enabled 0 = rdrf interrupt requests disabled ilie ? idle line interrupt enable bit this read/write bit enables sci interrupt requests when the idle bit becomes set. reset clears the ilie bit. 1 = idle interrupt requests enabled 0 = idle interrupt requests disabled te ? transmit enable bit setting this read/write bit begins the transmission by sending a preamble of 10 or 11 logic 1s from the transmit shift register to the pd1/tdo pin. reset clears the te bit. 1 = transmission enabled 0 = transmission disabled re ? receive enable bit setting this read/write bit enables the receiver. clearing the re bit disables the receiver and receiver interrupts but does not affect the receiver interrupt flags. reset clears the re bit. 1 = receiver enabled 0 = receiver disabled rwu ? receiver wakeup enable bit this read/write bit puts the receiver in a standby state. typically, data transmitted to the receiver clears the rwu bit and returns the receiver to normal operation. the wake bit in sccr1 determines whether an f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface (sci) sci i/o registers mc68hc705c8a ? rev. 3 technical data motorola serial communications interface (sci) idle input or an address mark brings the receiver out of the standby state. reset clears the rwu bit. 1 = standby state 0 = normal operation sbk ? send break bit setting this read/write bit continuously transmits break codes in the form of 10-bit or 11-bit groups of logic 0s. clearing the sbk bit stops the break codes and transmits a logic 1 as a start bit. reset clears the sbk bit. 1 = break codes being transmitted 0 = no break codes being transmitted 10.6.4 sci status register the sci status register (scsr) shown in figure 10-8 contains flags to signal these conditions: transfer of scdr data to transmit shift register complete transmission complete transfer of receive shift register data to scdr complete receiver input idle receiver overrun noisy data framing error address: $0010 bit 7654321bit 0 read: tdre tc rdrf idle or nf fe write: reset:1100000u = unimplemented u = unaffected figure 10-8. sci status register (scsr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data mc68hc705c8a ? rev. 3 134 serial communications interface (sci) serial communications interface (sci) tdre ? transmit data register empty bit this clearable, read-only bit is set when the data in the scdr transfers to the transmit shift register. tdre generates an interrupt request if the tie bit in sccr2 is also set. clear the tdre bit by reading the scsr with tdre set and then writing to the scdr. reset sets the tdre bit. software must initialize the tdre bit to logic 0 to avoid an instant interrupt request when turning on the transmitter. 1 = scdr data transferred to transmit shift register 0 = scdr data not transferred to transmit shift register tc ? transmission complete bit this clearable, read-only bit is set when the tdre bit is set and no data, preamble, or break character is being transmitted. tc generates an interrupt request if the tcie bit in sccr2 is also set. clear the tc bit by reading the scsr with tc set and then writing to the scdr. reset sets the tc bit. software must initialize the tc bit to logic 0 to avoid an instant interrupt request when turning on the transmitter. 1 = no transmission in progress 0 = transmission in progress rdrf ? receive data register full bit this clearable, read-only bit is set when the data in the receive shift register transfers to the sci data register. rdrf generates an interrupt request if the rie bit in sccr2 is also set. clear the rdrf bit by reading the scsr with rdrf set and then reading the scdr. reset clears the rdrf bit. 1 = received data available in scdr 0 = received data not available in scdr idle ? receiver idle bit this clearable, read-only bit is set when 10 or 11 consecutive logic 1s appear on the receiver input. idle generates an interrupt request if the ilie bit in sccr2 is also set. clear the idle bit by reading the scsr with idle set, and then reading the scdr. reset clears the idle bit. 1 = receiver input idle 0 = receiver input not idle f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface (sci) sci i/o registers mc68hc705c8a ? rev. 3 technical data motorola serial communications interface (sci) or ? receiver overrun bit this clearable, read-only bit is set if the scdr is not read before the receive shift register receives the next word. or generates an interrupt request if the rie bit in sccr2 is also set. the data in the shift register is lost, but the data already in the scdr is not affected. clear the or bit by reading the scsr with or set and then reading the scdr. reset clears the or bit. 1 = receiver shift register full and rdrf = 1 0 = no receiver overrun nf ? receiver noise flag bit this clearable, read-only bit is set when noise is detected in data received in the sci data register. clear the nf bit by reading the scsr and then reading the scdr. reset clears the nf bit. 1 = noise detected in scdr 0 = no noise detected in scdr fe ? receiver framing error bit this clearable, read-only flag is set when a logic 0 is located where a stop bit should be in the character shifted into the receive shift register. if the received word causes both a framing error and an overrun error, the or bit is set and the fe bit is not set. clear the fe bit by reading the scsr and then reading the scdr. reset clears the fe bit. 1 = framing error 0 = no framing error f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data mc68hc705c8a ? rev. 3 136 serial communications interface (sci) serial communications interface (sci) 10.6.5 baud rate register the baud rate register shown in figure 10-9 selects the baud rate for both the receiver and the transmitter. scp1 and scp0 ? sci prescaler select bits these read/write bits control prescaling of the baud rate generator clock, as shown in table 10-1 . resets clear both scp1 and scp0. address: $000d bit 7654321bit 0 read: scp1 scp0 scr2 scr1 scr0 write: reset:uu0 0uuuu = unimplemented u = unaffected figure 10-9. baud rate register (baud) table 10-1. baud rate generator clock prescaling scp[1:0] baud rate generator clock 00 internal clock 1 01 internal clock 3 10 internal clock 4 11 internal clock 13 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface (sci) sci i/o registers mc68hc705c8a ? rev. 3 technical data motorola serial communications interface (sci) scr2 ? scr0 ? sci baud rate select bits these read/write bits select the sci baud rate, as shown in table 10-2 . reset has no effect on the scr2 ? scr0 bits. table 10-3 shows all possible sci baud rates derived from crystal frequencies of 2 mhz, 4 mhz, and 4.194304 mhz. table 10-2. baud rate selection scr[2:1:0] sci baud rate (baud) 000 prescaled clock 1 001 prescaled clock 2 010 prescaled clock 4 011 prescaled clock 8 100 prescaled clock 16 101 prescaled clock 32 110 prescaled clock 64 111 prescaled clock 128 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data mc68hc705c8a ? rev. 3 138 serial communications interface (sci) serial communications interface (sci) table 10-3. baud rate selection examples scp[1:0] scr[2:1:0] sci baud rate f osc = 2 mhz f osc = 4 mhz f osc = 4.194304 mhz 00 000 62.50 kbaud 125 kbaud 131.1 kbaud 00 001 31.25 kbaud 62.50 kbaud 65.54 kbaud 00 010 15.63 kbaud 31.25 kbaud 32.77 kbaud 00 011 7813 baud 15.63 kbaud 16.38 kbaud 00 100 3906 baud 7813 baud 8192 baud 00 101 1953 baud 3906 baud 4096 baud 00 110 976.6 baud 1953 baud 2048 baud 00 111 488.3 baud 976.6 baud 1024 baud 01 000 20.83 kbaud 41.67 kbaud 43.69 kbaud 01 001 10.42 kbaud 20.83 kbaud 21.85 kbaud 01 010 5208 baud 10.42 kbaud 10.92 kbaud 01 011 2604 baud 5208 baud 5461 baud 01 100 1302 baud 2604 baud 2731 baud 01 101 651.0 baud 1302 baud 1365 baud 01 110 325.5 baud 651.0 baud 682.7 baud 01 111 162.8 baud 325.5 baud 341.3 baud 10 000 15.63 kbaud 31.25 kbaud 32.77 kbaud 10 001 7813 baud 15.63 kbaud 16.38 kbaud 10 010 3906 baud 7813 baud 8192 baud 10 011 1953 baud 3906 baud 4906 baud 10 100 976.6 baud 1953 baud 2048 baud 10 101 488.3 baud 976.6 baud 1024 baud 10 110 244.1 baud 488.3 baud 512.0 baud 10 111 122.1 baud 244.1 baud 256.0 baud 11 000 4808 baud 9615 baud 10.08 kbaud 11 001 2404 baud 4808 baud 5041 baud 11 010 1202 baud 2404 baud 2521 baud 11 011 601.0 baud 1202 baud 1260 baud 11 100 300.5 baud 601.0 baud 630.2 baud 11 101 150.2 baud 300.5 baud 315.1 baud 11 110 75.12 baud 150.2 baud 157.5 baud 11 111 37.56 baud 75.12 baud 78.77 baud f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc705c8a ? rev. 3 technical data motorola serial peripheral interface (spi) technical data ? mc68hc705c8a section 11. serial peripheral interface (spi) 11.1 contents 11.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 11.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 11.4 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 11.4.1 pin functions in master mode . . . . . . . . . . . . . . . . . . . . . .143 11.4.2 pin functions in slave mode . . . . . . . . . . . . . . . . . . . . . . .144 11.5 multiple-spi systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 11.6 serial clock polarity and phase . . . . . . . . . . . . . . . . . . . . . . .146 11.7 spi error conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 11.7.1 mode fault error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147 11.7.2 write collision error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 11.7.3 overrun error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 11.8 spi interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148 11.9 spi i/o registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 11.9.1 spi data register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 11.9.2 spi control register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 11.9.3 spi status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 11.2 introduction the serial peripheral interface (spi) module allows full-duplex, synchronous, serial communication with peripheral devices. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data mc68hc705c8a ? rev. 3 140 serial peripheral interface (spi) serial peripheral interface (spi) 11.3 features features of the spi include: full-duplex operation master and slave modes four programmable master mode frequencies (1.05 mhz maximum) 2.1-mhz maximum slave mode frequency serial clock with programmable polarity and phase end of transmission interrupt flag write collision error flag bus contention error flag figure 11-1 shows the structure of the spi module. figure 11-2 is a summary of the spi input/output (i/o) registers. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface (spi) features mc68hc705c8a ? rev. 3 technical data motorola serial peripheral interface (spi) figure 11-1. spi block diagram spi shift register divider spcr ($000a) 7 6 5 4 3 2 1 0 pd4/ sck pd3/ mosi 2 32 6 4 select spi control s m m s internal clock (xtal 2) pin control logic pd2/ miso spsr ($000b) spif wcol modf request spr1 spr0 spdr ($000c) spi interrupt internal data bus spi clock (master) clock logic mstr spe m s mstr spe dwom spie spe dwom mstr cpha cpol spr1 spr0 shift clock spie pd5/ ss f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data mc68hc705c8a ? rev. 3 142 serial peripheral interface (spi) serial peripheral interface (spi) 11.4 operation the master/slave spi allows full-duplex, synchronous, serial communication between the microcontroller unit (mcu) and peripheral devices, including other mcus. as the 8-bit shift register of a master spi transmits each byte to another device, a byte from the receiving device enters the master spi shift register. a clock signal from the master spi synchronizes data transmission. only a master spi can initiate transmissions. software begins the transmission from a master spi by writing to the spi data register (spdr). the spdr does not buffer data being transmitted from the spi. data written to the spdr goes directly into the shift register and begins the transmission immediately under the control of the serial clock. the transmission ends after eight cycles of the serial clock when the spi flag (spif) becomes set. at the same time that spif becomes set, the data shifted into the master spi from the receiving device transfers to the spdr. the spdr buffers data being received by the spi. before the master spi sends the next byte, software must clear the spif bit by reading the spsr and then accessing the spdr. addr. register name bit 7 6 5 4 3 2 1 bit 0 $000a spi control register (spcr) see page 149. read: spie spe mstr cpol cpha spr1 spr0 write: reset: 0 0 0 u u u u $000b spi status register (spsr) see page 151. read: spif wcol modf write: reset: 0 0 0 $000c spi data register (spdr) see page 149. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: unaffected by reset = unimplemented u = unaffected figure 11-2. spi i/o register summary f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface (spi) operation mc68hc705c8a ? rev. 3 technical data motorola serial peripheral interface (spi) in a slave spi, data enters the shift register under the control of the serial clock from the master spi. after a byte enters the shift register of a slave spi, it transfers to the spdr. to prevent an overrun condition, slave software must then read the byte in the spdr before another byte enters the shift register and is ready to transfer to the spdr. figure 11-3 shows how a master spi exchanges data with a slave spi. figure 11-3. master/slave connections 11.4.1 pin functions in master mode setting the mstr bit in the spi control register (spcr) configures the spi for operation in master mode. the master-mode functions of the spi pins are: pd4/sck (serial clock) ? in master mode, the pd4/sck pin is the synchronizing clock output. pd3/mosi (master output, slave input) ? in master mode, the pd3/mosi pin is the serial output. pd2/miso (master input, slave output) ? in master mode, the pd2/miso pin is configured as the serial input. pd5/ss (slave select) ? in master mode, the pd5/ss pin protects against driver contention caused by the simultaneous operation of two spis in master mode. a logic 0 on the pd5/ss pin of a master spi disables the spi, clears the mstr bit, and sets the mode-fault flag (modf). spi shift register 7 6 5 4 3 2 1 0 spi shift register 7 6 5 4 3 2 1 0 spdr ($000c) spdr ($000c) pd3/mosi pd2/miso pd5/ss pd4/sck master mcu slave mcu f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data mc68hc705c8a ? rev. 3 144 serial peripheral interface (spi) serial peripheral interface (spi) 11.4.2 pin functions in slave mode clearing the mstr bit in the spcr configures the spi for operation in slave mode. the slave-mode functions of the spi pins are: pd4/sck (serial clock) ? in slave mode, the pd4/sck pin is the input for the synchronizing clock signal from the master spi. pd3/mosi (master output, slave input) ? in slave mode, the pd3/mosi pin is the serial input. pd2/miso (master input, slave output) ? in slave mode, the pd2/miso pin is the serial output. pd5/ss (slave select) ? in slave mode, the pd5/ss pin enables the spi for data and serial clock reception from a master spi. when cpha = 0, the shift clock is the or of ss with sck. in this clock phase mode, ss must go high between successive characters in an spi message. when cpha = 1, ss may be left low for several spi characters. in cases with only one spi slave mcu, the slave mcu ss line can be tied to v ss as long as cpha = 1 clock modes are used. the wcol flag bit can be improperly set when attempting the first transmission after a reset if these conditions are present: mstr = 0, cpol = 0, cpha = 1, ss pin = 0, and sck pin = 1. the reset states of the cpol and cpha bits are 0 and 1, respectively. under normal operating conditions (cpol = 0, cpha = 1), the sck input will be low. the incorrect setting of the wcol bit can be prevented in two ways: 1. send a dummy transmission after reset, clear the wcol flag, and then proceed with the real transmission. 2. use the mstr bit in the spcr (spi control register). this is accomplished by setting the mstr bit at the same time the cpol and cpha bits are programmed to the desired logic levels. then, the data register can be written to if desired. after this, the mstr bit should be set to a logic 0, the spe (spi enable bit) should be set to a logic 1, and the cpol, cpha, spr1, and spr0 bits set to the desired logic levels. if this procedure is followed after a reset and before the first access to the spdr, the wcol flag will not be set. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface (spi) multiple-spi systems mc68hc705c8a ? rev. 3 technical data motorola serial peripheral interface (spi) example: lda #$1c ; mstr = 1, cpol = 1, cpha = 1, ; spr1 = spr0 = 0 sta spcr ; spi control register lda #$4c ; mstr = 0, spe = 1, cpol = 1, cpha = 1, ; spr1 = spr0 = 0 sta spcr ; spi control register 11.5 multiple-spi systems in a multiple-spi system, all pd4/sck pins are connected together, all pd3/mosi pins are connected together, and all pd2/miso pins are connected together. before a transmission, one spi is configured as master and the rest are configured as slaves. figure 11-4 is a block diagram showing a single master spi and three slave spis. figure 11-4. one master and three slaves block diagram figure 11-5 is another block diagram with two master/slave spis and three slave spis. pd2/miso pd3/mosi pd4/sck pd5/ss i/o 2 1 0 slave mcu 2 slave mcu 1 slave mcu 0 pd5/ss pd4/sck pd3/mosi pd2/miso master mcu port pd5/ss pd4/sck pd3/mosi pd2/miso pd5/ss pd4/sck pd3/mosi pd2/miso v dd f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data mc68hc705c8a ? rev. 3 146 serial peripheral interface (spi) serial peripheral interface (spi) figure 11-5. two master/slaves and three slaves block diagram 11.6 serial clock polarity and phase to accommodate the different serial communication requirements of peripheral devices, software can change the phase and polarity of the spi serial clock. the clock polarity bit (cpol) and the clock phase bit (cpha), both in the spcr, control the timing relationship between the serial clock and the transmitted data. figure 11-6 shows how the cpol and cpha bits affect the clock/data timing. figure 11-6. spi clock/data timing slave mcu 2 slave mcu 1 slave mcu 0 pd5/ss pd4/sck pd3/mosi pd2/miso master/slave pd5/ss pd4/sck pd3/mosi pd2/miso pd5/ss pd4/sck pd3/mosi pd2/miso pd2/miso pd3/mosi pd4/sck pd5/ss i/o 0 1 2 port 3 pd2/miso pd3/mosi pd4/sck pd5/ss i/o 0 1 2 port 3 mcu 1 master/slave mcu 2 msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 lsb sdo/sdi 1 0 1 0 ss 1 1 0 0 sck (d) sck (c) sck (b) sck (a) cpha cpol capture strobe f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface (spi) spi error conditions mc68hc705c8a ? rev. 3 technical data motorola serial peripheral interface (spi) 11.7 spi error conditions these conditions produce spi system errors: bus contention caused by multiple master spis (mode fault error) writing to the spdr during a transmission (write-collision error) failing to read the spdr before the next incoming byte sets the spif bit (overrun error) 11.7.1 mode fault error a mode fault error results when a logic 0 occurs on the pd5/ss pin of a master spi. the mcu takes these actions when a mode fault error occurs: puts the spi in slave mode by clearing the mstr bit disables the spi by clearing the spe bit sets the modf bit 11.7.2 write collision error writing to the spdr during a transmission causes a write collision error and sets the wcol bit in the spsr. either a master spi or a slave spi can generate a write collision error. master ? a master spi can cause a write collision error by writing to the spdr while the previously written byte is still being shifted out to the pd3/mosi pin. the error does not affect the transmission of the previously written byte, but the byte that caused the error is lost. slave ? a slave spi can cause a write collision error in either of two ways, depending on the state of the cpha bit: ? cpha = 0 ? a slave spi can cause a write collision error by writing to the spdr while the pd5/ss pin is at logic 0. the error does not affect the byte in the spdr, but the byte that caused the error is lost. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data mc68hc705c8a ? rev. 3 148 serial peripheral interface (spi) serial peripheral interface (spi) ? cpha = 1 ? a slave spi can cause a write collision error by writing to the spdr while receiving a transmission, that is, between the first active sck edge and the end of the eighth sck cycle. the error does not affect the transmission from the master spi, but the byte that caused the error is lost. 11.7.3 overrun error failing to read the byte in the spdr before a subsequent byte enters the shift register causes an overrun condition. in an overrun condition, all incoming data is lost until software clears spif. the overrun condition has no flag. 11.8 spi interrupts the spif bit in the spsr indicates a byte has shifted into or out of the spdr. the spif bit is a source of spi interrupt requests. the spi interrupt enable bit (spie) in the spcr is the local mask for spif interrupts. the modf bit in the spsr indicates a mode error and is a source of spi interrupt requests. the modf bit is set when a logic 0 occurs on the pd5/ss pin while the mstr bit is set. the spi interrupt enable bit (spie) in the spcr is the local mask for modf interrupts. 11.9 spi i/o registers these input/output (i/o) registers control and monitor spi operation: spi data register (spdr) spi control register (spcr) spi status register (spsr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface (spi) spi i/o registers mc68hc705c8a ? rev. 3 technical data motorola serial peripheral interface (spi) 11.9.1 spi data register the spdr shown in figure 11-7 is the read buffer for characters received by the spi. writing a byte to the spdr places the byte directly into the spi shift register. 11.9.2 spi control register enables spi interrupt requests enables the spi configures the spi as master or slave selects serial clock polarity, phase, and frequency spie ? spi interrupt enable bit this read/write bit enables spi interrupts. reset clears the spie bit. 1 = spi interrupts enabled 0 = spi interrupts disabled address: $000c bit 7654321bit 0 read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset: unaffected by reset figure 11-7. spi data register (spdr) address: $000a bit 7654321bit 0 read: spie spe mstr cpol cpha spr1 spr0 write: reset:0 0 0uuuu = unimplemented u = unaffected figure 11-8. spi control register (spcr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data mc68hc705c8a ? rev. 3 150 serial peripheral interface (spi) serial peripheral interface (spi) spi ? spi enable bit this read/write bit enables the spi. reset clears the spe bit. 1 = spi enabled 0 = spi disabled mstr ? master bit this read/write bit selects master mode operation or slave mode operation. reset clears the mstr bit. 1 = master mode 0 = slave mode cpol ? clock polarity bit this read/write bit determines the logic state of the pd4/sck pin between transmissions. to transmit data between spis, the spis must have identical cpol bits. reset has no effect on the cpol bit. 1 = pd4/sck pin at logic 1 between transmissions 0 = pd4/sck pin at logic 0 between transmissions cpha ? clock phase bit this read/write bit controls the timing relationship between the serial clock and spi data. to transmit data between spis, the spis must have identical cpha bits. when cpha = 0, the pd5/ss pin of the slave spi must be set to logic 1 between bytes. reset has no effect on the cpha bit. 1 = edge following first active edge on pd4/sck latches data 0 = first active edge on pd4/sck latches data spr1 and spr0 ? spi clock rate bits these read/write bits select the master mode serial clock rate, as shown in table 11-1 . the spr1 and spr0 bits of a slave spi have no effect on the serial clock. reset has no effect on spr1 and spr0. table 11-1. spi clock rate selection spr[1:0] spi clock rate 00 internal clock 2 01 internal clock 4 10 internal clock 16 11 internal clock 32 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface (spi) spi i/o registers mc68hc705c8a ? rev. 3 technical data motorola serial peripheral interface (spi) 11.9.3 spi status register the spsr shown in figure 11-9 contains flags to signal these conditions: spi transmission complete write collision mode fault spif ? spi flag this clearable, read-only bit is set each time a byte shifts out of or into the shift register. spif generates an interrupt request if the spie bit in the spcr is also set. clear spif by reading the spsr with spif set and then reading or writing the spdr. reset clears the spif bit. 1 = transmission complete 0 = transmission not complete wcol ? write collision bit this clearable, read-only flag is set when software writes to the spdr while a transmission is in progress. clear the wcol bit by reading the spsr with wcol set and then reading or writing the spdr. reset clears wcol. 1 = invalid write to spdr 0 = no invalid write to spdr address: $000b bit 7654321bit 0 read: spif wcol modf write: reset: 0 0 0 = unimplemented figure 11-9. spi status register (spsr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data mc68hc705c8a ? rev. 3 152 serial peripheral interface (spi) serial peripheral interface (spi) modf ? mode fault bit this clearable, read-only bit is set when a logic 0 occurs on the pd5/ss pin while the mstr bit is set. modf generates an interrupt request if the spie bit is also set. clear the modf bit by reading the spsr with modf set and then writing to the spcr. reset clears modf. 1 = pd5/ss pulled low while mstr bit set 0 = pd5/ss not pulled low while mstr bit set f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc705c8a ? rev. 3 technical data motorola instruction set technical data ? mc68hc705c8a section 12. instruction set 12.1 contents 12.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 12.3 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 12.3.1 inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 12.3.2 immediate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 12.3.3 direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 12.3.4 extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 12.3.5 indexed, no offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 12.3.6 indexed, 8-bit offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 12.3.7 indexed, 16-bit offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 12.3.8 relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 12.4 instruction types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 12.4.1 register/memory instructions. . . . . . . . . . . . . . . . . . . . . . .158 12.4.2 read-modify-write instructions . . . . . . . . . . . . . . . . . . . . . 159 12.4.3 jump/branch instructions. . . . . . . . . . . . . . . . . . . . . . . . . . 160 12.4.4 bit manipulation instructions . . . . . . . . . . . . . . . . . . . . . . .162 12.4.5 control instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 12.5 instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 12.6 opcode map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data mc68hc705c8a ? rev. 3 154 instruction set instruction set 12.2 introduction the mcu instruction set has 62 instructions and uses eight addressing modes. the instructions include all those of the m146805 cmos family plus one more: the unsigned multiply (mul) instruction. the mul instruction allows unsigned multiplication of the contents of the accumulator (a) and the index register (x). the high-order product is stored in the index register, and the low-order product is stored in the accumulator. 12.3 addressing modes the cpu uses eight addressing modes for flexibility in accessing data. the addressing modes provide eight different ways for the cpu to find the data required to execute an instruction. the eight addressing modes are: inherent immediate direct extended indexed, no offset indexed, 8-bit offset indexed, 16-bit offset relative f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . instruction set addressing modes mc68hc705c8a ? rev. 3 technical data motorola instruction set 12.3.1 inherent inherent instructions are those that have no operand, such as return from interrupt (rti) and stop (stop). some of the inherent instructions act on data in the cpu registers, such as set carry flag (sec) and increment accumulator (inca). inherent instructions require no operand address and are one byte long. 12.3.2 immediate immediate instructions are those that contain a value to be used in an operation with the value in the accumulator or index register. immediate instructions require no operand address and are two bytes long. the opcode is the first byte, and the immediate data value is the second byte. 12.3.3 direct direct instructions can access any of the first 256 memory locations with two bytes. the first byte is the opcode, and the second is the low byte of the operand address. in direct addressing, the cpu automatically uses $00 as the high byte of the operand address. 12.3.4 extended extended instructions use three bytes and can access any address in memory. the first byte is the opcode; the second and third bytes are the high and low bytes of the operand address. when using the motorola assembler, the programmer does not need to specify whether an instruction is direct or extended. the assembler automatically selects the shortest form of the instruction. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data mc68hc705c8a ? rev. 3 156 instruction set instruction set 12.3.5 indexed, no offset indexed instructions with no offset are 1-byte instructions that can access data with variable addresses within the first 256 memory locations. the index register contains the low byte of the effective address of the operand. the cpu automatically uses $00 as the high byte, so these instructions can address locations $0000 ? $00ff. indexed, no offset instructions are often used to move a pointer through a table or to hold the address of a frequently used ram or i/o location. 12.3.6 indexed, 8-bit offset indexed, 8-bit offset instructions are 2-byte instructions that can access data with variable addresses within the first 511 memory locations. the cpu adds the unsigned byte in the index register to the unsigned byte following the opcode. the sum is the effective address of the operand. these instructions can access locations $0000 ? $01fe. indexed 8-bit offset instructions are useful for selecting the kth element in an n-element table. the table can begin anywhere within the first 256 memory locations and could extend as far as location 510 ($01fe). the k value is typically in the index register, and the address of the beginning of the table is in the byte following the opcode. 12.3.7 indexed, 16-bit offset indexed, 16-bit offset instructions are 3-byte instructions that can access data with variable addresses at any location in memory. the cpu adds the unsigned byte in the index register to the two unsigned bytes following the opcode. the sum is the effective address of the operand. the first byte after the opcode is the high byte of the 16-bit offset; the second byte is the low byte of the offset. indexed, 16-bit offset instructions are useful for selecting the kth element in an n-element table anywhere in memory. as with direct and extended addressing, the motorola assembler determines the shortest form of indexed addressing. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . instruction set instruction types mc68hc705c8a ? rev. 3 technical data motorola instruction set 12.3.8 relative relative addressing is only for branch instructions. if the branch condition is true, the cpu finds the effective branch destination by adding the signed byte following the opcode to the contents of the program counter. if the branch condition is not true, the cpu goes to the next instruction. the offset is a signed, two ? s complement byte that gives a branching range of ? 128 to +127 bytes from the address of the next location after the branch instruction. when using the motorola assembler, the programmer does not need to calculate the offset, because the assembler determines the proper offset and verifies that it is within the span of the branch. 12.4 instruction types the mcu instructions fall into five categories: register/memory instructions read-modify-write instructions jump/branch instructions bit manipulation instructions control instructions f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data mc68hc705c8a ? rev. 3 158 instruction set instruction set 12.4.1 register/memory instructions these instructions operate on cpu registers and memory locations. most of them use two operands. one operand is in either the accumulator or the index register. the cpu finds the other operand in memory. table 12-1. register/memory instructions instruction mnemonic add memory byte and carry bit to accumulator adc add memory byte to accumulator add and memory byte with accumulator and bit test accumulator bit compare accumulator cmp compare index register with memory byte cpx exclusive or accumulator with memory byte eor load accumulator with memory byte lda load index register with memory byte ldx multiply mul or accumulator with memory byte ora subtract memory byte and carry bit from accumulator sbc store accumulator in memory sta store index register in memory stx subtract memory byte from accumulator sub f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . instruction set instruction types mc68hc705c8a ? rev. 3 technical data motorola instruction set 12.4.2 read-modify-write instructions these instructions read a memory location or a register, modify its contents, and write the modified value back to the memory location or to the register. note: do not use read-modify-write operations on write-only registers. table 12-2. read-modify-write instructions instruction mnemonic arithmetic shift left (same as lsl) asl arithmetic shift right asr bit clear bclr (1) 1. unlike other read-modify-write instructions, bclr and bset use only direct addressing. bit set bset (1) clear register clr complement (one ? s complement) com decrement dec increment inc logical shift left (same as asl) lsl logical shift right lsr negate (two ? s complement) neg rotate left through carry bit rol rotate right through carry bit ror test for negative or zero tst (2) 2. tst is an exception to the read-modify-write sequence because it does not write a replacement value. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data mc68hc705c8a ? rev. 3 160 instruction set instruction set 12.4.3 jump/branch instructions jump instructions allow the cpu to interrupt the normal sequence of the program counter. the unconditional jump instruction (jmp) and the jump-to-subroutine instruction (jsr) have no register operand. branch instructions allow the cpu to interrupt the normal sequence of the program counter when a test condition is met. if the test condition is not met, the branch is not performed. the brclr and brset instructions cause a branch based on the state of any readable bit in the first 256 memory locations. these 3-byte instructions use a combination of direct addressing and relative addressing. the direct address of the byte to be tested is in the byte following the opcode. the third byte is the signed offset byte. the cpu finds the effective branch destination by adding the third byte to the program counter if the specified bit tests true. the bit to be tested and its condition (set or clear) is part of the opcode. the span of branching is from ? 128 to +127 from the address of the next location after the branch instruction. the cpu also transfers the tested bit to the carry/borrow bit of the condition code register. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . instruction set instruction types mc68hc705c8a ? rev. 3 technical data motorola instruction set table 12-3. jump and branch instructions instruction mnemonic branch if carry bit clear bcc branch if carry bit set bcs branch if equal beq branch if half-carry bit clear bhcc branch if half-carry bit set bhcs branch if higher bhi branch if higher or same bhs branch if irq pin high bih branch if irq pin low bil branch if lower blo branch if lower or same bls branch if interrupt mask clear bmc branch if minus bmi branch if interrupt mask set bms branch if not equal bne branch if plus bpl branch always bra branch if bit clear brclr branch never brn branch if bit set brset branch to subroutine bsr unconditional jump jmp jump to subroutine jsr f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data mc68hc705c8a ? rev. 3 162 instruction set instruction set 12.4.4 bit manipulation instructions the cpu can set or clear any writable bit in the first 256 bytes of memory, which includes i/o registers and on-chip ram locations. the cpu can also test and branch based on the state of any bit in any of the first 256 memory locations. table 12-4. bit manipulation instructions instruction mnemonic bit clear bclr branch if bit clear brclr branch if bit set brset bit set bset f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . instruction set instruction types mc68hc705c8a ? rev. 3 technical data motorola instruction set 12.4.5 control instructions these instructions act on cpu registers and control cpu operation during program execution. table 12-5. control instructions instruction mnemonic clear carry bit clc clear interrupt mask cli no operation nop reset stack pointer rsp return from interrupt rti return from subroutine rts set carry bit sec set interrupt mask sei stop oscillator and enable irq pin stop software interrupt swi transfer accumulator to index register tax transfer index register to accumulator txa stop cpu clock and enable interrupts wait f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data mc68hc705c8a ? rev. 3 164 instruction set instruction set 12.5 instruction set summary table 12-6. instruction set summary (sheet 1 of 6) source form operation description effect on ccr address mode opcode operand cycles hinzc adc # opr adc opr adc opr adc opr ,x adc opr ,x adc ,x add with carry a (a) + (m) + (c) ? imm dir ext ix2 ix1 ix a9 b9 c9 d9 e9 f9 ii dd hh ll ee ff ff 2 3 4 5 4 3 add # opr add opr add opr add opr ,x add opr ,x add ,x add without carry a (a) + (m) ? imm dir ext ix2 ix1 ix ab bb cb db eb fb ii dd hh ll ee ff ff 2 3 4 5 4 3 and # opr and opr an d opr and opr ,x and opr ,x and ,x logical and a (a) (m) ?? ? imm dir ext ix2 ix1 ix a4 b4 c4 d4 e4 f4 ii dd hh ll ee ff ff 2 3 4 5 4 3 asl opr asla aslx asl opr ,x asl ,x arithmetic shift left (same as lsl) ?? dir inh inh ix1 ix 38 48 58 68 78 dd ff 5 3 3 6 5 asr opr asra asrx asr opr ,x asr ,x arithmetic shift right ?? dir inh inh ix1 ix 37 47 57 67 77 dd ff 5 3 3 6 5 bcc rel branch if carry bit clear pc (pc) + 2 + rel ? c = 0 ????? rel 24 rr 3 bclr n opr clear bit n mn 0 ????? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 11 13 15 17 19 1b 1d 1f dd dd dd dd dd dd dd dd 5 5 5 5 5 5 5 5 bcs rel branch if carry bit set (same as blo) pc (pc) + 2 + rel ? c = 1 ????? rel 25 rr 3 beq rel branch if equal pc (pc) + 2 + rel ? z = 1 ????? rel 27 rr 3 bhcc rel branch if half-carry bit clear pc (pc) + 2 + rel ? h = 0 ????? rel 28 rr 3 bhcs rel branch if half-carry bit set pc (pc) + 2 + rel ? h = 1 ????? rel 29 rr 3 bhi rel branch if higher pc (pc) + 2 + rel ? c z = 0 ????? rel 22 rr 3 bhs rel branch if higher or same pc (pc) + 2 + rel ? c = 0 ????? rel 24 rr 3 c b0 b7 0 b0 b7 c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . instruction set instruction set summary mc68hc705c8a ? rev. 3 technical data motorola instruction set bih rel branch if irq pin high pc (pc) + 2 + rel ? irq = 1 ????? rel 2f rr 3 bil rel branch if irq pin low pc (pc) + 2 + rel ? irq = 0 ????? rel 2e rr 3 bit # opr bit opr bit opr bit opr ,x bit opr ,x bit ,x bit test accumulator with memory byte (a) (m) ?? ? imm dir ext ix2 ix1 ix a5 b5 c5 d5 e5 f5 ii dd hh ll ee ff ff 2 3 4 5 4 3 blo rel branch if lower (same as bcs) pc (pc) + 2 + rel ? c = 1 ????? rel 25 rr 3 bls rel branch if lower or same pc (pc) + 2 + rel ? c z = 1 ????? rel 23 rr 3 bmc rel branch if interrupt mask clear pc (pc) + 2 + rel ? i = 0 ????? rel 2c rr 3 bmi rel branch if minus pc (pc) + 2 + rel ? n = 1 ????? rel 2b rr 3 bms rel branch if interrupt mask set pc (pc) + 2 + rel ? i = 1 ????? rel 2d rr 3 bne rel branch if not equal pc (pc) + 2 + rel ? z = 0 ????? rel 26 rr 3 bpl rel branch if plus pc (pc) + 2 + rel ? n = 0 ????? rel 2a rr 3 bra rel branch always pc (pc) + 2 + rel ? 1 = 1 ????? rel 20 rr 3 brclr n opr rel branch if bit n clear pc (pc) + 2 + rel ? mn = 0 ???? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 01 03 05 07 09 0b 0d 0f dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 brn rel branch never pc (pc) + 2 + rel ? 1 = 0 ????? rel 21 rr 3 brset n opr rel branch if bit n set pc (pc) + 2 + rel ? mn = 1 ???? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 00 02 04 06 08 0a 0c 0e dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 bset n opr set bit n mn 1 ????? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 10 12 14 16 18 1a 1c 1e dd dd dd dd dd dd dd dd 5 5 5 5 5 5 5 5 bsr rel branch to subroutine pc (pc) + 2; push (pcl) sp (sp) ? 1; push (pch) sp (sp) ? 1 pc (pc) + rel ????? rel ad rr 6 clc clear carry bit c 0 ???? 0inh98 2 cli clear interrupt mask i 0 ? 0 ??? inh 9a 2 table 12-6. instruction set summary (sheet 2 of 6) source form operation description effect on ccr address mode opcode operand cycles hinzc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data mc68hc705c8a ? rev. 3 166 instruction set instruction set clr opr clra clrx clr opr ,x clr ,x clear byte m $00 a $00 x $00 m $00 m $00 ?? 01 ? dir inh inh ix1 ix 3f 4f 5f 6f 7f dd ff 5 3 3 6 5 cmp # opr cmp opr cmp opr cmp opr ,x cmp opr ,x cmp ,x compare accumulator with memory byte (a) ? (m) ?? imm dir ext ix2 ix1 ix a1 b1 c1 d1 e1 f1 ii dd hh ll ee ff ff 2 3 4 5 4 3 com opr coma comx com opr ,x com ,x complement byte (one ? s complement) m (m ) = $ff ? (m) a (a ) = $ff ? (a) x (x ) = $ff ? (x) m (m ) = $ff ? (m) m (m ) = $ff ? (m) ?? 1 dir inh inh ix1 ix 33 43 53 63 73 dd ff 5 3 3 6 5 cpx # opr cpx opr cpx opr cpx opr ,x cpx opr ,x cpx ,x compare index register with memory byte (x) ? (m) ?? imm dir ext ix2 ix1 ix a3 b3 c3 d3 e3 f3 ii dd hh ll ee ff ff 2 3 4 5 4 3 dec opr deca decx dec opr ,x dec ,x decrement byte m (m) ? 1 a (a) ? 1 x (x) ? 1 m (m) ? 1 m (m) ? 1 ?? ? dir inh inh ix1 ix 3a 4a 5a 6a 7a dd ff 5 3 3 6 5 eor # opr eor opr eor opr eor opr ,x eor opr ,x eor ,x exclusive or accumulator with memory byte a (a) (m) ?? ? imm dir ext ix2 ix1 ix a8 b8 c8 d8 e8 f8 ii dd hh ll ee ff ff 2 3 4 5 4 3 inc opr inca incx inc opr ,x inc ,x increment byte m (m) + 1 a (a) + 1 x (x) + 1 m (m) + 1 m (m) + 1 ?? ? dir inh inh ix1 ix 3c 4c 5c 6c 7c dd ff 5 3 3 6 5 jmp opr jmp opr jmp opr ,x jmp opr ,x jmp ,x unconditional jump pc jump address ????? dir ext ix2 ix1 ix bc cc dc ec fc dd hh ll ee ff ff 2 3 4 3 2 table 12-6. instruction set summary (sheet 3 of 6) source form operation description effect on ccr address mode opcode operand cycles hinzc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . instruction set instruction set summary mc68hc705c8a ? rev. 3 technical data motorola instruction set jsr opr jsr opr jsr opr ,x jsr opr ,x jsr ,x jump to subroutine pc (pc) + n (n = 1, 2, or 3) push (pcl); sp (sp) ? 1 push (pch); sp (sp) ? 1 pc effective address ????? dir ext ix2 ix1 ix bd cd dd ed fd dd hh ll ee ff ff 5 6 7 6 5 lda # opr lda opr lda opr lda opr ,x lda opr ,x lda ,x load accumulator with memory byte a (m) ?? ? imm dir ext ix2 ix1 ix a6 b6 c6 d6 e6 f6 ii dd hh ll ee ff ff 2 3 4 5 4 3 ldx # opr ldx opr ldx opr ldx opr ,x ldx opr ,x ldx ,x load index register with memory byte x (m) ?? ? imm dir ext ix2 ix1 ix ae be ce de ee fe ii dd hh ll ee ff ff 2 3 4 5 4 3 lsl opr lsla lslx lsl opr ,x lsl ,x logical shift left (same as asl) ?? dir inh inh ix1 ix 38 48 58 68 78 dd ff 5 3 3 6 5 lsr opr lsra lsrx lsr opr ,x lsr ,x logical shift right ?? 0 dir inh inh ix1 ix 34 44 54 64 74 dd ff 5 3 3 6 5 mul unsigned multiply x : a (x) (a) 0 ??? 0inh42 1 1 neg opr nega negx neg opr ,x neg ,x negate byte (two ? s complement) m ? (m) = $00 ? (m) a ? (a) = $00 ? (a) x ? (x) = $00 ? (x) m ? (m) = $00 ? (m) m ? (m) = $00 ? (m) ?? dir inh inh ix1 ix 30 40 50 60 70 dd ff 5 3 3 6 5 nop no operation ????? inh 9d 2 ora # opr ora opr ora opr ora opr ,x ora opr ,x ora ,x logical or accumulator with memory a (a) (m) ?? ? imm dir ext ix2 ix1 ix aa ba ca da ea fa ii dd hh ll ee ff ff 2 3 4 5 4 3 rol opr rola rolx rol opr ,x rol ,x rotate byte left through carry bit ?? dir inh inh ix1 ix 39 49 59 69 79 dd ff 5 3 3 6 5 table 12-6. instruction set summary (sheet 4 of 6) source form operation description effect on ccr address mode opcode operand cycles hinzc c b0 b7 0 b0 b7 c 0 c b0 b7 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data mc68hc705c8a ? rev. 3 168 instruction set instruction set ror opr rora rorx ror opr ,x ror ,x rotate byte right through carry bit ?? dir inh inh ix1 ix 36 46 56 66 76 dd ff 5 3 3 6 5 rsp reset stack pointer sp $00ff ????? inh 9c 2 rti return from interrupt sp (sp) + 1; pull (ccr) sp (sp) + 1; pull (a) sp (sp) + 1; pull (x) sp (sp) + 1; pull (pch) sp (sp) + 1; pull (pcl) inh 80 9 rts return from subroutine sp (sp) + 1; pull (pch) sp (sp) + 1; pull (pcl) ????? inh 81 6 sbc # opr sbc opr sbc opr sbc opr ,x sbc opr ,x sbc ,x subtract memory byte and carry bit from accumulator a (a) ? (m) ? (c) ?? imm dir ext ix2 ix1 ix a2 b2 c2 d2 e2 f2 ii dd hh ll ee ff ff 2 3 4 5 4 3 sec set carry bit c 1 ???? 1inh99 2 sei set interrupt mask i 1 ? 1 ??? inh 9b 2 sta opr sta opr sta opr ,x sta opr ,x sta ,x store accumulator in memory m (a) ?? ? dir ext ix2 ix1 ix b7 c7 d7 e7 f7 dd hh ll ee ff ff 4 5 6 5 4 stop stop oscillator and enable irq pin ? 0 ??? inh 8e 2 stx opr stx opr stx opr ,x stx opr ,x stx ,x store index register in memory m (x) ?? ? dir ext ix2 ix1 ix bf cf df ef ff dd hh ll ee ff ff 4 5 6 5 4 sub # opr sub opr sub opr sub opr ,x sub opr ,x sub ,x subtract memory byte from accumulator a (a) ? (m) ?? imm dir ext ix2 ix1 ix a0 b0 c0 d0 e0 f0 ii dd hh ll ee ff ff 2 3 4 5 4 3 swi software interrupt pc (pc) + 1; push (pcl) sp (sp) ? 1; push (pch) sp (sp) ? 1; push (x) sp (sp) ? 1; push (a) sp (sp) ? 1; push (ccr) sp (sp) ? 1; i 1 pch interrupt vector high byte pcl interrupt vector low byte ? 1 ??? inh 83 1 0 tax transfer accumulator to index register x (a) ????? inh 97 2 table 12-6. instruction set summary (sheet 5 of 6) source form operation description effect on ccr address mode opcode operand cycles hinzc b0 b7 c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . instruction set opcode map mc68hc705c8a ? rev. 3 technical data motorola instruction set 12.6 opcode map see table 12-7 . tst opr tsta tstx tst opr ,x tst ,x test memory byte for negative or zero (m) ? $00 ?? ? dir inh inh ix1 ix 3d 4d 5d 6d 7d dd ff 4 3 3 5 4 txa transfer index register to accumulator a (x) ????? inh 9f 2 wait stop cpu clock and enable interrupts ? ??? inh 8f 2 a accumulator opr operand (one or two bytes) c carry/borrow flag pc program counter ccr condition code register pch program counter high byte dd direct address of operand pcl program counter low byte dd rr direct address of operand and relative offset of branch instruction rel relative addressing mode dir direct addressing mode rel relative program counter offset byte ee ff high and low bytes of offset in indexed, 16-bit offset addressing rr relative program counter offset byte ext extended addressing mode sp stack pointer ff offset byte in indexed, 8-bit offset addressing x index register h half-carry flag z zero flag hh ll high and low bytes of operand address in extended addressing # immediate value i interrupt mask logical and ii immediate operand byte logical or imm immediate addressing mode logical exclusive or inh inherent addressing mode ( ) contents of ix indexed, no offset addressing mode ? ( ) negation (two ? s complement) ix1 indexed, 8-bit offset addressing mode loaded with ix2 indexed, 16-bit offset addressing mode ? if m memory location : concatenated with n negative flag set or cleared n any bit ? not affected table 12-6. instruction set summary (sheet 6 of 6) source form operation description effect on ccr address mode opcode operand cycles hinzc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data mc68hc705c8a ? rev. 3 170 instruction set instruction set table 12-7. opcode map bit manipulation branch read-modify-write control register/memory dir dir rel dir inh inh ix1 ix inh inh imm dir ext ix2 ix1 ix 012345 6789ab cdef 0 5 brset0 3dir 5 bset0 2dir 3 bra 2rel 5 neg 2dir 3 nega 1inh 3 negx 1inh 6 neg 2ix1 5 neg 1ix 9 rti 1inh 2 sub 2imm 3 sub 2dir 4 sub 3ext 5 sub 3ix2 4 sub 2ix1 3 sub 1ix 0 1 5 brclr0 3dir 5 bclr0 2dir 3 brn 2rel 6 rts 1inh 2 cmp 2imm 3 cmp 2dir 4 cmp 3ext 5 cmp 3ix2 4 cmp 2ix1 3 cmp 1ix 1 2 5 brset1 3dir 5 bset1 2dir 3 bhi 2rel 11 mul 1inh 2 sbc 2imm 3 sbc 2dir 4 sbc 3ext 5 sbc 3ix2 4 sbc 2ix1 3 sbc 1ix 2 3 5 brclr1 3dir 5 bclr1 2dir 3 bls 2rel 5 com 2dir 3 coma 1inh 3 comx 1inh 6 com 2ix1 5 com 1ix 10 swi 1inh 2 cpx 2imm 3 cpx 2dir 4 cpx 3ext 5 cpx 3ix2 4 cpx 2ix1 3 cpx 1ix 3 4 5 brset2 3dir 5 bset2 2dir 3 bcc 2rel 5 lsr 2dir 3 lsra 1inh 3 lsrx 1inh 6 lsr 2ix1 5 lsr 1ix 2 and 2imm 3 and 2dir 4 and 3ext 5 and 3ix2 4 and 2ix1 3 and 1ix 4 5 5 brclr2 3dir 5 bclr2 2dir 3 bcs/blo 2rel 2 bit 2imm 3 bit 2dir 4 bit 3ext 5 bit 3ix2 4 bit 2ix1 3 bit 1ix 5 6 5 brset3 3dir 5 bset3 2dir 3 bne 2rel 5 ror 2dir 3 rora 1inh 3 rorx 1inh 6 ror 2ix1 5 ror 1ix 2 lda 2imm 3 lda 2dir 4 lda 3ext 5 lda 3ix2 4 lda 2ix1 3 lda 1ix 6 7 5 brclr3 3dir 5 bclr3 2dir 3 beq 2rel 5 asr 2dir 3 asra 1inh 3 asrx 1inh 6 asr 2ix1 5 asr 1ix 2 tax 1inh 4 sta 2dir 5 sta 3ext 6 sta 3ix2 5 sta 2ix1 4 sta 1ix 7 8 5 brset4 3dir 5 bset4 2dir 3 bhcc 2rel 5 asl/lsl 2dir 3 asla/lsla 1inh 3 aslx/lslx 1inh 6 asl/lsl 2ix1 5 asl/lsl 1ix 2 clc 1inh 2 eor 2imm 3 eor 2dir 4 eor 3ext 5 eor 3ix2 4 eor 2ix1 3 eor 1ix 8 9 5 brclr4 3dir 5 bclr4 2dir 3 bhcs 2rel 5 rol 2dir 3 rola 1inh 3 rolx 1inh 6 rol 2ix1 5 rol 1ix 2 sec 1inh 2 adc 2imm 3 adc 2dir 4 adc 3ext 5 adc 3ix2 4 adc 2ix1 3 adc 1ix 9 a 5 brset5 3dir 5 bset5 2dir 3 bpl 2rel 5 dec 2dir 3 deca 1inh 3 decx 1inh 6 dec 2ix1 5 dec 1ix 2 cli 1inh 2 ora 2imm 3 ora 2dir 4 ora 3ext 5 ora 3ix2 4 ora 2ix1 3 ora 1ix a b 5 brclr5 3dir 5 bclr5 2dir 3 bmi 2rel 2 sei 1inh 2 add 2imm 3 add 2dir 4 add 3ext 5 add 3ix2 4 add 2ix1 3 add 1ix b c 5 brset6 3dir 5 bset6 2dir 3 bmc 2rel 5 inc 2dir 3 inca 1inh 3 incx 1inh 6 inc 2ix1 5 inc 1ix 2 rsp 1inh 2 jmp 2dir 3 jmp 3ext 4 jmp 3ix2 3 jmp 2ix1 2 jmp 1ix c d 5 brclr6 3dir 5 bclr6 2dir 3 bms 2rel 4 tst 2dir 3 tsta 1inh 3 tstx 1inh 5 tst 2ix1 4 tst 1ix 2 nop 1inh 6 bsr 2rel 5 jsr 2dir 6 jsr 3ext 7 jsr 3ix2 6 jsr 2ix1 5 jsr 1ix d e 5 brset7 3dir 5 bset7 2dir 3 bil 2rel 2 stop 1inh 2 ldx 2imm 3 ldx 2dir 4 ldx 3ext 5 ldx 3ix2 4 ldx 2ix1 3 ldx 1ix e f 5 brclr7 3dir 5 bclr7 2dir 3 bih 2rel 5 clr 2dir 3 clra 1inh 3 clrx 1inh 6 clr 2ix1 5 clr 1ix 2 wait 1inh 2 txa 1inh 4 stx 2dir 5 stx 3ext 6 stx 3ix2 5 stx 2ix1 4 stx 1ix f inh = inherent rel = relative imm = immediate ix = indexed, no offset dir = direct ix1 = indexed, 8-bit offset ext = extended ix2 = indexed, 16-bit offset 0 msb of opcode in hexadecimal lsb of opcode in hexadecimal 0 5 brset0 3dir number of cycles opcode mnemonic number of bytes/addressing mode lsb msb lsb msb lsb msb f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc705c8a ? rev. 3 technical data motorola electrical specifications technical data ? mc68hc705c8a section 13. electrical specifications 13.1 contents 13.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 13.3 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 13.4 operating temperature range. . . . . . . . . . . . . . . . . . . . . . . .173 13.5 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 13.6 power considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 13.7 5.0-volt dc electrical characteristics. . . . . . . . . . . . . . . . . . .175 13.8 3.3-volt dc electrical characteristics . . . . . . . . . . . . . . . . . .176 13.9 5.0-volt control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 13.10 3.3-volt control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 13.11 5.0-volt serial peripheral interface (spi) timing . . . . . . . . . .185 13.12 3.3-volt serial peripheral interface (spi) timing . . . . . . . . . .187 13.2 introduction this section contains electrical and timing specifications. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data mc68hc705c8a ? rev. 3 172 electrical specifications electrical specifications 13.3 maximum ratings maximum ratings are the extreme limits to which the mcu can be exposed without permanently damaging it. the mcu contains circuitry to protect the inputs against damage from high static voltages; however, do not apply voltages higher than those shown in the table here. keep v in and v out within the range v ss (v in or v out ) v dd . connect unused inputs to the appropriate voltage level, either v ss or v dd . note: this device is not guaranteed to operate properly at the maximum ratings. refer to 13.7 5.0-volt dc electrical characteristics and 13.8 3.3-volt dc electrical characteristics for guaranteed operating conditions. rating (1) 1. voltages referenced to v ss symbol value unit supply voltage v dd ? 0.3 to +7.0 v input voltage v in v ss ? 0.3 to v dd +0.3 v programming voltage v pp v dd ? 0.3 to 16.0 bootstrap mode (irq pin only) v in v ss ? 0.3 to 2 x v dd + 0.3 v current drain per pin excluding v dd and v ss i25ma storage temperature range t stg ? 65 to +150 c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical specifications operating temperature range mc68hc705c8a ? rev. 3 technical data motorola electrical specifications 13.4 operating temperature range 13.5 thermal characteristics figure 13-1. equivalent test load rating (1) 1. voltages referenced to v ss symbol value unit operating temperature range (2) mc68hc705c8acb mc68hc705c8acfb mc68hc705c8acfs mc68hc705c8acp mc68hc705c8acfn mc68hc705c8acfs 2. c = extended temperature range ( ? 40 c to + 85 c) p = plastic dual in-line package (pdip) b = plastic shrink dual in-line package (sdip) s = ceramic dual in-line package (cerdip) fn = plastic-leaded chip carrier (plcc) fb = quad flat pack (qfp) fs = ceramic-leaded chip carrier (clcc) t a t l to t h ? 40 to + 85 c characteristic symbol value unit thermal resistance plastic dual in-line package (dip) ceramic dual in-line package (cerdip) plastic leaded chip carrier (plcc) quad flat pack (qfp) plastic shrink dip (sdip) ja 60 50 70 95 60 c/w v dd c r2 r1 test point (see table) (see table) (see table) v dd = 4.5 v pins r1 r2 c pa7 ? pa0 pb7 ? pb0 pc7 ? pc0 pd4 ? pd1 3.26 k ? 2.38 k ? 50 pf v dd = 3.0 v pins r1 r2 c pa7 ? pa0 pb7 ? pb0 pc7 ? pc0 pd4 ? pd1 10.91 k ? 6.32 k ? 50 pf pd7, pd5, pd0 6 k ? 6 k ? 200 pf f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data mc68hc705c8a ? rev. 3 174 electrical specifications electrical specifications 13.6 power considerations the average chip junction temperature, t j , in c can be obtained from: t j = t a + (p d x ja )(1) where: t a = ambient temperature in c ja = package thermal resistance, junction to ambient in c/w p d = p int + p i/o p int = i cc v cc = chip internal power dissipation p i/o = power dissipation on input and output pins (user-determined) for most applications, p i/o < p int and can be neglected. ignoring p i/o , the relationship between p d and t j is approximately: (2) solving equations (1) and (2) for k gives: = p d x (t a + 273 c) + ja x (p d ) 2 (3) where k is a constant pertaining to the particular part. k can be determined from equation (3) by measuring p d (at equilibrium) for a known t a . using this value of k, the values of p d and t j can be obtained by solving equations (1) and (2) iteratively for any value of t a . p d = t j + 273 c k f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical specifications 5.0-volt dc electrical characteristics mc68hc705c8a ? rev. 3 technical data motorola electrical specifications 13.7 5.0-volt dc electrical characteristics characteristic (1) 1. v dd = 5 v 10%; v ss = 0 vdc, t a = t l to t h , unless otherwise noted symbol min typ (2) 2. typical values reflect average measurements at midpoint of voltage range at 25 c. max unit output voltage, i load 10.0 a v ol v oh ? v dd ? 0.1 ? ? 0.1 ? v output high voltage i load = ? 0.8 ma, pa7 ? pa0, pb7 ? pb0, pc6 ? pc0, tcmp (see figure 13-2 ) i load = ? 1.6 ma, pd4 ? pd1 (see figure 13-3 ) i load = ? 5.0 ma, pc7 v oh v dd ? 0.8 ? ? ? ? ? ? v output low voltage (see figure 13-4 ) i load = 1.6 ma pa7 ? pa0, pb7 ? pb0, pc6 ? pc0, pd4 ? pd1 i load = 20 ma, pc7 v ol ? ? ? ? 0.4 0.4 v input high voltage pa7 ? pa0, pb7 ? pb0, pc7 ? pc0, pd5 ? pd0, pd7, tcap, irq , reset , osc1 v ih 0.7 x v dd ? v dd v input low voltage pa7 ? pa0, pb7 ? pb0, pc7 ? pc0, pd5 ? pd0, pd7, tcap, irq , reset , osc1 v il v ss ? 0.2 x v dd v eprom programming voltage v pp 14.5 14.75 15.0 v eprom/otprom programming current i pp ? 510ma user mode current i pp ?? 10 ma data-retention mode (0 c to 70 c) v rm 2.0 ?? v supply current (3) run (4) wait (5) stop (6) 25 c ? 40 c to +85 c 3. i dd measured with port b pullup devices disabled. 4. run (operating) i dd measured using external square wave clock source (f osc = 4.2 mhz). all inputs 0.2 v from rail. no dc loads. less than 50 pf on all outputs. c l = 20 pf on osc2. osc2 capacitance linearly affects run i dd . 5. wait i dd measured using external square wave clock source (f osc = 4.2 mhz). all inputs 0.2 v from rail. no dc loads. less than 50 pf on all outputs. c l = 20 pf on osc2. v il = 0.2 v, v ih = v dd ? 0.2 v. all ports configured as inputs. spi and sci disabled. if spi and sci enabled, add 10% current draw. osc2 capacitance linearly affects wait i dd . 6. stop i dd measured with osc1 = v dd . all ports configured as inputs. v il = 0.2 v, v ih = v dd ? 0.2 v. i dd ? ? ? ? 5.0 1.95 5.0 5.0 7.0 3.0 50 50 ma ma a a i/o ports hi-z leakage current pa7 ? pa0, pb7 ? pb0, pc7 ? pc0, pd4 ? pd1, pd7, reset i il ?? 10 a input current, irq , tcap, osc1, pd0, pd5 i in ?? 1 a capacitance ports (as input or output) reset , irq , tcap, pd0 ? pd5, pd7 c out c in ? ? ? ? 12 8 pf f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data mc68hc705c8a ? rev. 3 176 electrical specifications electrical specifications 13.8 3.3-volt dc electrical characteristics characteristic (1) 1. v dd = 3.3 v 10%; v ss = 0 vdc, t a = t l to t h , unless otherwise noted symbol min typ (2) 2. typical values at midpoint of voltage range, 25 c only. max unit output voltage, i load 10.0 a v ol v oh ? v dd ? 0.1 ? ? 0.1 ? v output high voltage i load = ? 0.2 ma pa7 ? pa0, pb7 ? pb0, pc6 ? pc0, tcmp (see figure 13-2 ) i load = ? 0.4 ma pd4 ? pd1 (see figure 13-3 ) i load = ? 1.5 ma pc7 v oh v dd ? 0.3 ? ? ? ? ? ? v output low voltage (see figure 13-4 ) i load = 0.4 ma pa7 ? pa0, pb7 ? pb0, pc6 ? pc0, pd4 ? pd1 i load = 6.0 ma pc7 v ol ? ? ? ? 0.3 0.3 v input high voltage pa7 ? pa0, pb7 ? pb0, pc7 ? pc0, pd5 ? pd0, pd7, tcap, irq , reset , osc1 v ih 0.7 x v dd ? v dd v input low voltage pa7 ? pa0, pb7 ? pb0, pc7 ? pc0, pd5 ? pd0, pd7, tcap, irq , reset , osci v il v ss ? 0.2 x v dd v data-retention mode (0 c to 70 c) v rm 2.0 ?? v supply current (3) run (4) wait (5) stop (6) 3. i dd measured with port b pullup devices disabled. 4. run (operating) i dd measured using external square wave clock source (f osc = 2.0 mhz). all inputs 0.2 v from rail. no dc loads. less than 50 pf on all outputs. c l = 20 pf on osc2. osc2 capacitance linearly affects run i dd. 5. wait i dd measured using external square wave clock source (f osc = 2.0 mhz). all inputs 0.2 v from rail. no dc loads. less than 50 pf on all outputs. c l = 20 pf on osc2. v il = 0.2 v, v ih = v dd ? 0.2 v. all ports configured as inputs. spi and sci disabled. if spi and sci enabled, add 10% current draw. osc2 capacitance linearly affects wait i dd . 6. stop i dd measured with osc1 = v dd . all ports configured as inputs. v il = 0.2 v; v ih = v dd ? 0.2 v. i dd ? ? ? 1.53 0.711 2.0 3.0 1.0 20 ma ma a i/o ports hi-z leakage current pa7 ? pa0, pb7 ? pb0, pc7 ? pc0, pd4 ? pd1, pd7, reset i il ?? 10 a input current irq , tcap, osc1, pd5, pd0 i in ?? 1 a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical specifications 3.3-volt dc electrical characteristics mc68hc705c8a ? rev. 3 technical data motorola electrical specifications figure 13-2. typical voltage compared to current 0 1.0 2.0 3.0 4.0 5.0 00.60.8 0.2 0.4 v dd ? v oh (volts) i oh (ma) (a) v oh versus i oh for ports a, b, pc6 ? pc0, and tcmp v d d = 5 . 0 v see note 1 see note 2 1. at v dd = 5.0 v, devices are specified and tested for (v dd ? v oh ) notes: 800 mv @ i oh = ? 0.8 ma. v d d = 3 . 0 v 2. at v dd = 3.3 v, devices are specified and tested for (v dd ? v oh ) 300 mv @ i oh = ? 0.2 ma. 0.8 0.2 0 2.0 4.0 6.0 8.0 00.6 0.2 0.4 v dd ? v oh (volts) i oh (ma) v d d = 5 . 0 v (b) v oh versus i oh for pd4 ? pd1 see note 1 see note 2 v d d = 3 . 0 v 1. at v dd = 5.0 v, devices are specified and tested for notes: (v dd ? v oh ) 800 mv @ i oh = ? 1.6 ma. 2. at v dd = 3.3 v, devices are specified and tested for (v dd ? v oh ) 300 mv @ i oh = ? 0.4 ma. 1.6 0.4 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data mc68hc705c8a ? rev. 3 178 electrical specifications electrical specifications figure 13-2. typical voltage compared to current (continued) 0 1.0 2.0 3.0 4.0 5.0 00.30.4 0.1 0.2 v ol (volts) i ol (ma) 6.0 v d d = 5 . 0 v v d d = 3 . 0 v (c) v ol versus i ol for all ports except pc7 see note 1 see note 2 1. at v dd = 5.0 v, devices are specified and tested for notes: v ol 400 mv @ i ol = 1.6 ma. 2. at v dd = 3.3 v, devices are specified and tested for v ol 300 mv @ i ol = 0.4 ma. 1.6 0.4 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical specifications 3.3-volt dc electrical characteristics mc68hc705c8a ? rev. 3 technical data motorola electrical specifications figure 13-3. typical current versus internal frequency for run and wait modes i d d ( m a ) 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 0.0 0.5 1.0 1.5 2.0 internal frequency 1 t cyc (mhz) 2.0 (a) wait mode v d d = 5 . 0 v v d d = 3 . 3 v i d d ( m a ) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 0.0 0.5 1.0 1.5 2.0 internal frequency 1 t cyc (mhz) 5.0 (b) run mode v d d = 5 . 0 v v d d = 3 . 3 v 5.5 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data mc68hc705c8a ? rev. 3 180 electrical specifications electrical specifications figure 13-4. total current drain versus frequency supply current (i dd ) 1.0 ma 1.5 ma 2.0 ma 2.5 ma 3.0 ma 0 250 khz 500 khz 750 khz 1 mhz internal clock frequency (xtal 2) 0 500 ma t = ? 40 c to 85 c v dd = 3.3 v 10% stop i dd (20 a) r u n ( o p e r a t i n g ) i d d w a i t i d d (a) maximum current drain versus frequency @ 3.3 v 10 % supply current (i dd ) 1.0 ma 2.0 ma 3.0 ma 4.0 ma 5.0 ma 0 500 khz 1 mhz 1.5 mhz 2 mhz internal clock frequency (xtal 2) 0 t = ? 40 c to 85 c v dd = 5.0 v 10% stop i dd (50 a) 6.0 ma 7.0 ma r u n ( o p e r a t i n g ) i d d w a i t i d d (b) maximum current drain versus frequency @ 5 v 10% f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical specifications 5.0-volt control timing mc68hc705c8a ? rev. 3 technical data motorola electrical specifications 13.9 5.0-volt control timing characteristic (1) 1. v dd = 5.0 vdc 10%, v ss = 0 vdc; t a = t l to t h symbol min max unit frequency of operation crystal option external clock option f osc ? dc 4.2 4.2 mhz internal operating frequency crystal (f osc 2) external clock (f osc 2) f op ? dc 2.1 2.1 mhz cycle time (see figure 13-7 ) t cyc 480 ? ns crystal oscillator startup time (see figure 13-7 ) t oxov ? 100 ms stop recovery startup time (crystal oscillator) (see figure 13-6 ) t ilch ? 100 ms reset pulse width (see figure 13-7 ) t rl 8 ? t cyc timer resolution (2) input capture pulse width (see figure 13-5 ) input capture pulse period (see figure 13-5 ) 2. since a 2-bit prescaler in the timer must count four internal cycles (t cyc ), this is the limiting minimum factor in determining the timer resolution. t resl t th , t tl t tltl 4.0 125 (3) 3. the minimum period, t tltl , should not be less than the number of cycle times it takes to execute the capture interrupt ser- vice routine plus 24 t cyc . ? ? ? t cyc ns t cyc interrupt pulse width low (edge-triggered) (see figure 4-2. external interrupt timing ) t ilih 125 ? ns interrupt pulse period (see figure 4-2. external interrupt timing ) t ilil (4) 4. the minimum period, t ilil , should not be less than the number of cycle times it takes to execute the interrupt service routine plus 19 t cyc . ? t cyc osc1 pulse width t oh , t ol 90 ? ns f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data mc68hc705c8a ? rev. 3 182 electrical specifications electrical specifications 13.10 3.3-volt control timing figure 13-5. timer relationships characteristic (1) symbol min max unit frequency of operation crystal option external clock option f osc ? dc 2.0 2.0 mhz internal operating frequency crystal (f osc 2) external clock (f osc 2) f op ? dc 1.0 1.0 mhz cycle time (see figure 13-7 ) t cyc 1000 ? ns crystal oscillator startup time (see figure 13-7 ) t oxov ? 100 ms stop recovery startup time (crystal oscillator) (see figure 13-6 ) t ilch ? 100 ms reset pulse width, excluding power-up (see figure 13-7 ) t rl 8 ? t cyc timer resolution (2) input capture pulse width (see figure 13-5 ) input capture pulse period (see figure 13-5 ) t resl t th , t tl t tltl 4.0 250 (3) ? ? ? t cyc ns t cyc interrupt pulse width low (edge-triggered) (see figure 4-2. external interrupt timing ) t ilih 250 ? ns interrupt pulse period (see figure 4-2. external interrupt timing ) t ilil (4) ? t cyc osc1 pulse width t oh , t ol 200 ? ns 1. v dd = 3.3 vdc 0.3 vdc, v ss = 0 vdc; t a = t l to t h 2. since a 2-bit prescaler in the timer must count four internal cycles (t cyc ), this is the limiting minimum factor in determining the timer resolution. 3. the minimum period, t tltl , should not be less than the number of cycle times it takes to execute the capture interrupt ser- vice routine plus 24 t cyc . 4. the minimum period, t ilil , should not be less than the number of cycle times it takes to execute the interrupt service routine plus 19 t cyc . t tltl * external signal t th * t tl * * refer to timer resolution data in figure 13-6 and figure 13-7 . (tcap pin 37) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical specifications 3.3-volt control timing mc68hc705c8a ? rev. 3 technical data motorola electrical specifications figure 13-6. stop recovery timing diagram 1ffe 1ffe 1ffe 1ffe 1fff (4) t ilch 4064 t cyc t ilih t rl notes: 1. represents the internal gating of the osc1 pin 2. irq pin edge-sensitive option 3. irq pin level and edge-sensitive option 4. reset vector address shown for timing example reset or interrupt vector fetch osc1 (1) reset irq (2) irq (3) internal clock internal address bus f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data mc68hc705c8a ? rev. 3 184 electrical specifications electrical specifications figure 13-7. power-on reset and external reset timing diagram pch pcl osc1 reset internal processor internal address bus 1ffe 1fff v dd v dd threshold (1-2 v typical) t vddr t rl internal data bus 1ffe 1ffe 1ffe 1ffe new pc 1fff * osc1 line is not meant to represent frequency. it is o nly used to represent time. ** internal timing signal and bus information are not avai lable externally. *** the next rising edge of the internal processor clock f ollowing the rising edge of reset initiates the reset sequence. new new pcl pch new pc clock op code op code t cyc t oxov * * * * ** *** f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical specifications 5.0-volt serial peripheral interface (spi) timing mc68hc705c8a ? rev. 3 technical data motorola electrical specifications 13.11 5.0-volt serial peripheral interface (spi) timing number (1) characteristic (2) symbol min max unit operating frequency master slave f op(m) f op(s) dc dc 0.5 2.1 f op mhz 1 cycle time master slave t cyc(m) t cyc(s) 2.0 480 ? ? t cyc ns 2 enable lead time master slave t lead(m) t lead(s) (3) 240 ? ? ns 3 enable lag time master slave t lag(m) t lag(s) (2) 720 ? ? ns 4 clock (sck) high time master slave t w(sckh)m t w(sckh)s 340 190 ? ? ns 5 clock (sck) low time master slave t w(sckl)m t w(sckl)s 340 190 ? ? ns 6 data setup time (inputs) master slave t su(m) t su(s) 100 100 ? ? ns 7 data hold time (inputs) master slave t h(m) t h(s) 100 100 ? ? ns 8 access time (4) slave t a 0 120 ns 9 disable time (5) slave t dis ? 240 ns 10 data valid time master (before capture edge) slave (after enable edge) (6) t v(m) t v(s) 0.25 ? ? 240 t cyc(m) ns continued f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data mc68hc705c8a ? rev. 3 186 electrical specifications electrical specifications 11 data hold time (outputs) master (after capture edge) slave (after enable edge) t ho(m) t ho(s) 0.25 0 ? ? t cyc(m) ns 12 rise time (7) spi outputs (sck, mosi, miso) spi inputs (sck, mosi, miso, ss ) t r(m) t r(s) ? ? 100 2.0 ns s 13 fall time (8) spi outputs (sck, mosi, miso) spi inputs (sck, mosi, miso, ss ) t f(m) t f(s) ? ? 100 2.0 ns s 1. numbers refer to dimensions in figure 13-8 and figure 13-9 . 2. v dd = 5.0 vdc 10% 3. signal production depends on software. 4. time to data active from high-impedance state 5. hold time to high-impedance state 6. with 200 pf on all spi pins 7. 20% of v dd to 70% of v dd ; c l = 200 pf 8. 70% of v dd to 20% of v dd ; c l = 200 pf number (1) characteristic (2) symbol min max unit f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical specifications 3.3-volt serial peripheral interface (spi) timing mc68hc705c8a ? rev. 3 technical data motorola electrical specifications 13.12 3.3-volt serial peripheral interface (spi) timing number (1) characteristic (2) symbol min max unit operating frequency master slave f op(m) f op(s) dc 0.5 2.1 f op mhz 1 cycle time master slave t cyc(m) t cyc(s) 2.0 1 ? ? t cyc ns 2 enable lead time master slave t lead(m) t lead(s) (3) 500 ? ? ns 3 enable lag time master slave t lag(m) t lag(s) (2) 1500 ? ? ns 4 clock (sck) high time master slave t w(sckh)m t w(sckh)s 720 400 ? ? ns 5 clock (sck) low time master slave t w(sckl)m t w(sckl)s 720 400 ? ? ns 6 data setup time (inputs) master slave t su(m) t su(s) 200 200 ? ? ns 7 data hold time (inputs) master slave t h(m) t h(s) 200 200 ? ? ns 8 access time (4) slave t a 0 250 ns 9 disable time (5) slave t dis ? 500 ns 10 data valid time master (before capture edge) slave (after enable edge) (6) t v(m) t v(s) 0.25 ? ? 500 t cyc(m) ns continued f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data mc68hc705c8a ? rev. 3 188 electrical specifications electrical specifications 11 data hold time (outputs) master (after capture edge) slave (after enable edge) t ho(m) t ho(s) 0.25 0 ? ? t cyc(m) ns 12 rise time (7) spi outputs (sck, mosi, miso) spi inputs (sck, mosi, miso, ss ) t r(m) t r(s) ? ? 200 2.0 ns s 13 fall time (8) spi outputs (sck, mosi, miso) spi inputs (sck, mosi, miso, ss ) t f(m) t f(s) ? ? 200 2.0 ns s 1. numbers refer to dimensions in figure 13-8 and figure 13-9 . 2. v dd = 3.3 vdc 10% 3. signal production depends on software. 4. time to data active from high-impedance state 5. hold time to high-impedance state 6. with 200 pf on all spi pins 7. 20% of v dd to 70% of v dd ; c l = 200 pf 8. 70% of v dd to 20% of v dd ; c l = 200 pf number (1) characteristic (2) symbol min max unit f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical specifications 3.3-volt serial peripheral interface (spi) timing mc68hc705c8a ? rev. 3 technical data motorola electrical specifications figure 13-8. spi master timing note note: this first clock edge is generated internally, but is not seen at the sck pin. ss pin of master held high. msb in ss input sck (cpol = 0) output sck (cpol = 1) output miso input mosi output note 4 5 5 1 13 12 4 12 13 bits 6 ? 1 lsb in master msb out bits 6 ? 1 master lsb out 10 13 11 10 12 11 7 6 note note: this last clock edge is generated internally, but is not seen at the sck pin. ss pin of master held high. msb in ss input sck (cpol = 0) output sck (cpol = 1) output miso input mosi output note 4 5 5 1 13 12 4 13 bits 6 ? 1 lsb in master msb out bits 6 ? 1 master lsb out 10 13 11 10 12 11 7 6 12 a) spi master timing (cpha = 0) b) spi master timing (cpha = 1) 12 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data mc68hc705c8a ? rev. 3 190 electrical specifications electrical specifications figure 13-9. spi slave timing note: not defined, but normally msb of character just received slave ss input sck (cpol = 0) (input sck (cpol = 1) input miso input mosi output 4 5 5 1 13 12 4 13 msb in bits 6 ? 1 8 6 10 11 11 12 note slave lsb out 9 3 lsb in 2 7 bits 6 ? 1 msb out note: not defined, but normally lsb of character previously transmitted slave ss input sck (cpol = 0) input sck (cpol = 1) input miso output mosi input 4 5 5 1 13 12 4 13 msb in bits 6 ? 1 8 6 10 11 12 note slave lsb out 9 3 lsb in 2 7 bits 6 ? 1 msb out 10 a) spi slave timing (cpha = 0) b) spi slave timing (cpha = 1) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc705c8a ? rev. 3 technical data motorola mechanical specifications technical data ? mc68hc705c8a section 14. mechanical specifications 14.1 contents 14.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 14.3 40-pin plastic dual in-line package (pdip). . . . . . . . . . . . . .192 14.4 40-pin ceramic dual in-line package (cerdip) . . . . . . . . . . .193 14.5 44-lead plastic-leaded chip carrier (plcc) . . . . . . . . . . . .194 14.6 44-lead ceramic-leaded chip carrier (clcc) . . . . . . . . . . .195 14.7 44-pin quad flat pack (qfp). . . . . . . . . . . . . . . . . . . . . . . . . 196 14.8 42-pin shrink dual in-line package (sdip) . . . . . . . . . . . . . .197 14.2 introduction package dimensions available at the time of this publication for the mc68hc705c8a are provided in this section. the packages are: 40-pin plastic dual in-line package (pdip) 40-pin ceramic dual-in-line package (cerdip) 44-lead plastic-leaded chip carrier (plcc) 44-lead ceramic-leaded chip carrier (clcc) 44-pin quad flat pack (qfp) 42-pin shrink dual in-line package (sdip) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data mc68hc705c8a ? rev. 3 192 mechanical specifications mechanical specifications 14.3 40-pin plastic dual in-line package (pdip) figure 14-1. mc68hc705c8ap package dimensions (case #711) 120 40 21 b a c seating plane d f g h k n m j l dim min max min max inches millimeters a 51.69 52.45 2.035 2.065 b 13.72 14.22 0.540 0.560 c 3.94 5.08 0.155 0.200 d 0.36 0.56 0.014 0.022 f 1.02 1.52 0.040 0.060 g 2.54 bsc 0.100 bsc h 1.65 2.16 0.065 0.085 j 0.20 0.38 0.008 0.015 k 2.92 3.43 0.115 0.135 l 15.24 bsc 0.600 bsc m 1 n 0.51 1.02 0.020 0.040 notes: 1.position tolerance of leads (d), shall bewithin 0.25 (0.010) at maximum material conditions, in relation to seating plane and each other. 2.dimension l to center of leads when formed parallel. 3.dimension b does not include mold flash. 1 0 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mechanical specifications 40-pin ceramic dual in-line package (cerdip) mc68hc705c8a ? rev. 3 technical data motorola mechanical specifications 14.4 40-pin ceramic dual in-line package (cerdip) figure 14-2. mc68hc705c8as package dimensions (case #734a) m l j dim min max min max millimeters inches a 2.020 2.096 51.31 53.23 b 0.500 0.610 12.70 15.94 c 0.160 0.240 4.06 6.09 d 0.015 0.022 0.38 0.55 f 0.050 0.065 1.27 1.65 g 0.100 bsc 2.54 bsc j 0.008 0.012 0.20 0.30 k 0.125 0.160 3.17 4.06 l 0.600 bsc 15.24 bsc m0 15 0 15 n 0.020 0.050 0.51 1.27 a 0.25(0.010) t t 40 pl d 1 40 20 21 a b g f k c n seating plane datum plane m m f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data mc68hc705c8a ? rev. 3 194 mechanical specifications mechanical specifications 14.5 44-lead plastic-leaded chip carrier (plcc) figure 14-3. mc68hc705c8afn package dimensions (case #777) -n- -l- -m- d y d k v w 1 44 brk b z u x view d-d s l-m m 0.007(0.180) n s t s l-m m 0.007(0.180) n s t g1 s l-m s 0.010 (0.25) n s t k1 f h s l-m m 0.007(0.180) n s t z g g1 r a e j view s c s l-m m 0.007(0.180) n s t s l-m m 0.007(0.180) n s t 0.004 (0.10) -t- seating plane view s dim min max min max millimeters inches a 0.685 0.695 17.40 17.65 b 0.685 0.695 17.40 17.65 c 0.165 0.180 4.20 4.57 e 0.090 0.110 2.29 2.79 f 0.013 0.019 0.33 0.48 g 0.050 bsc 1.27 bsc h 0.026 0.032 0.66 0.81 j 0.020 0.51 k 0.025 0.64 r 0.650 0.656 16.51 16.66 u 0.650 0.656 16.51 16.66 v 0.042 0.048 1.07 1.21 w 0.042 0.048 1.07 1.21 x 0.042 0.056 1.07 1.42 y 0.020 0.50 z 2 10 g1 0.610 0.630 15.50 16.00 k1 0.040 1.02 s l-m s 0.010 (0.25) n s t s l-m m 0.007(0.180) n s t 2 10 notes: 1. datums -l-, -m-, and -n- are determined where top of lead sholders exits plastic body at mold parting line. 2. dimension g1, true position to be measured at datum -t-, seating plane. 3. dimension r and u do not include mold flash. allowable mold flash is 0.010 (0.25) per side. 4. dimensioning and tolerancing per ansi y14.5m, 1982. 5. controlling dimension: inch. 6. the package top may be smaller than the package bottom by up to 0.012 (0.300). dimensions r and u are determined at the outermost extremes of the plastic body exclusive of the mold flash, tie bar burrs, gate burrs and interlead flash, but including any mismatch between the top and bottom of the plastic body. 7. diminsion h does not include dambar protrusion or intrusion. the dambar protusion(s) shall not cause the h diminsion to be greater than 0.037 (0.940198). the dambar intrusion(s) shall not cause the h diminision to smaller than 0.025 (0.635). f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mechanical specifications 44-lead ceramic-leaded chip carrier (clcc) mc68hc705c8a ? rev. 3 technical data motorola mechanical specifications 14.6 44-lead ceramic-leaded chip carrier (clcc) figure 14-4. mc68hc705c8afs package dimensions (case #777b) 17.40 17.40 4.20 2.29 0.33 0.66 0.51 0.64 16.51 6.94 16.51 1.07 1.07 --- 14.99 1.02 s l m 0.18 (0.007) n -p s s t b u g1 s l m 0.18 (0.007) n -p s s t s l m n -p s s t detail d-d -n- m l m 0.20 (0.008) n -p m m t -l- -p- 1 44 v d w s d y brk s l m 0.18 (0.007) n -p s s t s l m 0.18 (0.007) n -p s s t 0.10 (0.004) seating plane -t- j e r a g g1 s l s 0.25 (0.010) n -p s s t detail s c s l m 0.18 (0.007) n -p s s t s l m 0.18 (0.007) n -p s s t f s l m 0.18 (0.007) n -p s s t s l m 0.18 (0.007) n -p s s t h k k1 detail s dim min max min max inches millimeters a 17.65 0.685 0.695 b 17.65 0.685 0.695 c 4.57 0.165 0.180 e 2.79 0.090 0.110 f 0.48 0.013 0.019 g 1.27 bsc 0.050 bsc h 0.81 0.026 0.032 j --- 0.020 --- k --- 0.025 --- r 16.66 0.650 0.656 s 7.26 0.273 0.286 u 16.66 0.650 0.656 v 1.21 0.042 0.048 w 1.21 0.042 0.048 y 0.50 --- 0.020 g1 16.00 0.590 0.630 k1 --- 0.040 --- notes: 1. datums -l-, -n-, and -p- determined where top of lead shoulder exit body. 2. diminsion g1, true position to be measured at datum -t-, seating plane. 3. diminsions r and u do not include glass meniscus. allowable glass runout is 0.25 (0.010) per side. 4. diminsioning and tolerancing per ansi y14.5m, 1982. 0.25 (0.010) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data mc68hc705c8a ? rev. 3 196 mechanical specifications mechanical specifications 14.7 44-pin quad flat pack (qfp) figure 14-5. mc68hc705c8afb package dimensions (case #824a) notes: 1. 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. 2. controlling dimension: millimeter. 3. 3. datum plane -h- is located at bottom of lead and is coincident with the lead where the lead exits the plastic body at the bottom of the parting line. 4. 4. datums -a-, -b- and -d- to be determined at datum plane -h-. 5. 5. dimensions s and v to be determined at seating plane -c-. 6. 6. dimensions a and b do not include mold protrusion. allowable protrusion is 0.25 (0.010) per side. dimensions a and b do include mold mismatch and are determined at datum plane -h-. 7. 7. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the d dimension at maximum material condition. dambar cannot be located on the lower radius or the foot. l 33 34 23 22 44 111 12 detail a -d- -a- a s a-b m 0.20 (0.008) d s c s a-b m 0.20 (0.008) d s h 0.05 (0.002) a-b s b s a-b m 0.20 (0.008) d s c s a-b m 0.20 (0.008) d s h 0.05 (0.002) a-b v l -b- -c- seating plane m m e h g c -h- datum plane detail c 0.01 (0.004) m -h- datum plane t r k q w x detail c dim min max min max inches millimeters a 9.90 10.10 0.390 0.398 b 9.90 10.10 0.390 0.398 c 2.10 2.45 0.083 0.096 d 0.30 0.45 0.012 0.018 e 2.00 2.10 0.079 0.083 f 0.30 0.40 0.012 0.016 g 0.80 bsc 0.031 bsc h --- 0.25 --- 0.010 j 0.013 0.23 0.005 0.009 k 0.65 0.95 0.026 0.037 l 8.00 ref 0.315 ref m 5 10 5 10 n 0.13 0.17 0.005 0.007 q 0 7 0 7 r 0.13 0.30 0.005 0.012 s 12.95 13.45 0.510 0.530 t 0.13 --- 0.005 --- u 0 --- 0 --- v 12.95 13.45 0.510 0.530 w 0.40 --- 0.016 --- x 1.6 ref 0.063 ref detail a b b -a-, -b-, -d- s a-b m 0.20 (0.008) d s c f n section b-b j d base metal f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mechanical specifications 42-pin shrink dual in-line package (sdip) mc68hc705c8a ? rev. 3 technical data motorola mechanical specifications 14.8 42-pin shrink dual in-line package (sdip) figure 14-6. mc68hc705c8ab package dimensions (case #858) -b- -a- c d 42 pl f k g n j 42 pl m h l ! " ! # ! $# ! 121 42 22 -t- f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data mc68hc705c8a ? rev. 3 198 mechanical specifications mechanical specifications f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc705c8a ? rev. 3 technical data motorola ordering information technical data ? mc68hc705c8a section 15. ordering information 15.1 contents 15.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 15.3 mcu order numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .199 15.2 introduction this section contains ordering information for the available package types. 15.3 mcu order numbers table 15-1 lists the mc order numbers. table 15-1. mc68hc705c8a order numbers package type temperature range order number 40-pin plastic dual in-line package (pdip) ? 40 c to +85 c mc68hc705c8ac (1) p (2) 44-lead plastic-leaded chip carrier (plcc) ? 40 c to +85 c mc68hc705c8acfn (3) 44-lead ceramic-leaded chip carrier (clcc) ? 40 c to +85 c mc68hc705c8acfs (4) 40-pin windowed ceramic dip (cerdip) ? 40 c to +85 c mc68hc705c8acs (5) 44-pin quad flat pack (qfp) ? 40 c to +85 c mc68hc705c8acfb (6) 42-pin shrink dual in-line package (sdip) ? 40 c to +85 c mc68hc705c8acb (7) 1. c = extended temperature range ( ? 40 c to +85 c) 2. p = plastic dual in-line package (pdip) 3. fn = plastic-leaded chip carrier (plcc) 4. fs = ceramic-leaded chip carrier (clcc) 5. s = windowed ceramic dual in-line package (cerdip) 6. fb = quad flat pack (qfp) 7. b = shrink dual in-line package (sdip) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data mc68hc705c8a ? rev. 3 200 ordering information ordering information f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc705c8a ? rev. 3 technical data motorola mc68hsc705c8a technical data ? mc68hc705c8a appendix a. mc68hsc705c8a a.1 contents a.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 a.3 5.0-volt high-speed dc electrical characteristics. . . . . . . . .202 a.4 3.3-volt high-speed dc electrical characteristics . . . . . . . .203 a.5 5.0-volt high-speed control timing . . . . . . . . . . . . . . . . . . . .204 a.6 3.3-volt high-speed control timing . . . . . . . . . . . . . . . . . . . .204 a.7 5.0-volt high-speed spi timing . . . . . . . . . . . . . . . . . . . . . .205 a.8 3.3-volt high-speed spi timing. . . . . . . . . . . . . . . . . . . . . . .207 a.9 ordering information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 a.2 introduction the mc68hsc705c8a is an enhanced, high-speed version of the mc68hc705c8a, featuring a 4-mhz bus speed. the data in this document, mc68hc705c8a technical data rev. 3, applies to the mc68hsc705c8a with the exceptions given in this appendix. the computer operating properly (cop) mode bits (cm1 and cm0 in the cop control register) select the timeout period of the programmable cop watchdog, as shown in table a-1 . see figure 5-3. programmable cop control register (copcr) . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data mc68hc705c8a ? rev. 3 202 mc68hsc705c8a mc68hsc705c8a a.3 5.0-volt high-speed dc electrical characteristics table a-1. programmable cop timeout period selection cm1:cm0 cop timeout rate programmable cop timeout period f osc = 8.0 mhz f op = 4.0 mhz f osc = 4.0 mhz f op = 2.0 mhz f osc = 3.5795 mhz f op = 1.7897 mhz f osc = 2.0 mhz f op = 1.0 mhz 00 f op 2 15 8.192 ms 16.38 ms 18.31 ms 32.77 ms 01 f op 2 17 32.77 ms 65.54 ms 73.24 ms 131.07 ms 10 f op 2 19 131.07 ms 262.14 ms 292.95 ms 524.29 ms 11 f op 2 21 524.29 ms 1.048 s 1.172 s 2.097 s characteristic (1) 1. v dd = 5 v 10%; v ss = 0 vdc, t a = t l to t h , unless otherwise noted symbol min typ (2) 2. typical values reflect average measurements at midpoint of voltage range at 25 c. max unit output high voltage i load = ? 0.8 ma pa7 ? pa0, pb7 ? pb0, pc6 ? pc0, tcmp i load = ? 1.6 ma pd4 ? pd1 i load = ? 5.0 ma pc7 v oh v dd ? 0.8 ? ? ? ? ? ? v output low voltage i load = 1.6 ma pa7 ? pa0, pb7 ? pb0, pc6 ? pc0, pd4 ? pd1 i load = 20 ma pc7 v ol ? ? ? ? 0.4 0.4 v supply current (3) run (4) wait (5) stop (6) 25 c ? 40 c to +85 c 3. i dd measured with port b pullup devices disabled. 4. run (operating) i dd measured using external square wave clock source (f osc = 8.0 mhz). all inputs 0.2 v from rail. no dc loads. less than 50 pf on all outputs. c l = 20 pf on osc2. osc2 capacitance linearly affects run i dd . 5. wait i dd measured using external square wave clock source (f osc = 8.0 mhz). all inputs 0.2 v from rail. no dc loads. less than 50 pf on all outputs. c l = 20 pf on osc2. v il = 0.2 v, v ih = v dd ? 0.2 v. all ports configured as inputs. spi and sci disabled. if spi and sci enabled, add 10% current draw. osc2 capacitance linearly affects wait i dd . 6. stop i dd measured with osc1 = v dd . all ports configured as inputs. v il = 0.2 v, v ih = v dd ? 0.2 v. i dd ? ? ? ? 5.92 2.27 5 2.0 14 7.0 50 50 ma ma a a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hsc705c8a mc68hc705c8a ? rev. 3 technical data motorola mc68hsc705c8a a.4 3.3-volt high-speed dc electrical characteristics characteristic (1) 1. v dd = 3.3 v 10%; v ss = 0 vdc, t a = t l to t h , unless otherwise noted symbol min typ (2) 2. typical values reflect average measurements at midpoint of voltage range at 25 c. max unit output high voltage i load = ? 0.2 ma pa7 ? pa0, pb7 ? pb0, pc6 ? pc0, tcmp i load = ? 0.4 ma pd4 ? pd1 i load = ? 1.5 ma pc7 v oh v dd ? 0.3 ? ? ? ? ? ? v output low voltage i load = 0.4 ma pa7 ? pa0, pb7 ? pb0, pc6 ? pc0, pd4 ? pd1 i load = 6.0 ma pc7 v ol ? ? ? ? 0.3 0.3 v supply current (3) run (4) wait (5) stop (6) 3. i dd measured with port b pullup devices disabled. 4. run (operating) i dd measured using external square wave clock source (f osc = 4.2 mhz). all inputs 0.2 v from rail. no dc loads. less than 50 pf on all outputs. c l = 20 pf on osc2. osc2 capacitance linearly affects run i dd . 5. wait i dd measured using external square wave clock source (f osc = 4.2 mhz). all inputs 0.2 v from rail. no dc loads. less than 50 pf on all outputs. c l = 20 pf on osc2. v il = 0.2 v, v ih = v dd ? 0.2 v. all ports configured as inputs. spi and sci disabled. if spi and sci enabled, add 10% current draw. osc2 capacitance linearly affects wait i dd . 6. stop i dd measured with osc1 = v dd . all ports configured as inputs. v il = 0.2 v; v ih = v dd ? 0.2 v. i dd ? ? ? 1.91 0.915 2.0 6.0 2.0 20 ma ma a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data mc68hc705c8a ? rev. 3 204 mc68hsc705c8a mc68hsc705c8a a.5 5.0-volt high-speed control timing a.6 3.3-volt high-speed control timing characteristic (1) symbol min max unit oscillator frequency crystal oscillator external clock f osc ? dc 8.0 8.0 mhz internal operating frequency (f osc 2) crystal oscillator external clock f op ? dc 4.0 4.0 mhz cycle time t cyc 250 ? ns input capture pulse width t th , t tl 65 ? ns interrupt pulse width low (edge-triggered) t ilih 65 ? ns osc1 pulse width t oh , t ol 45 ? ns 1. v dd = 5 v 10%; v ss = 0 vdc, t a = t l to t h , unless otherwise noted characteristic (1) symbol min max unit oscillator frequency crystal oscillator external clock f osc ? dc 4.0 4.0 mhz internal operating frequency (f osc 2) crystal oscillator external clock f op ? dc 2.0 2.0 mhz cycle time t cyc 476 ? ns input capture pulse width t th , t tl 125 ? ns interrupt pulse width low (edge-triggered) t ilih 125 ? ns osc1 pulse width t oh , t ol 90 ? ns 1. v dd = 3.3 v 10%; v ss = 0 vdc, t a = t l to t h , unless otherwise noted f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hsc705c8a mc68hc705c8a ? rev. 3 technical data motorola mc68hsc705c8a a.7 5.0-volt high-speed spi timing diagram number (1) characteristic (2) symbol min max unit operating frequency master slave f op(s) f op(s) dc dc 0.5 4.0 f op mhz 1 cycle time master slave t cyc(m) t cyc(s) 2.0 250 ? ? t cyc ns 2 enable lead time master slave t lead(m) t lead(s) note (3) 125 ? ? ns 3 enable lag time master slave t lag(m) t lag(s) note (2) 375 ? ? ns 4 clock (sck) high time master slave t w(sckh)m t w(sckh)s 170 95 ? ? ns 5 clock (sck) low time master slave t w(sckl)m t w(sckl)s 170 95 ? ? ns 6 data setup time (inputs) master slave t su(m) t su(s) 50 50 ? ? ns 7 data hold time (inputs) master slave t h(m) t h(s) 50 50 ? ? ns 8 access time (4) slave t a 060ns 9 disable time (5) slave t dis ? 120 ns 10 data valid time master (before capture edge) slave (after enable edge) (6) t v(m) t v(s) 0.25 ? ? 120 t cyc(m) ns continued f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data mc68hc705c8a ? rev. 3 206 mc68hsc705c8a mc68hsc705c8a 11 data hold time (outputs) master (after capture edge) slave (after enable edge) t ho(m) t ho(s) 0.25 0 ? ? t cyc(m) ns 12 rise time (7) spi outputs (sck, mosi, miso) spi inputs (sck, mosi, miso, ss ) t rm t rs ? ? 50 2.0 ns s 13 fall time (8) spi outputs (sck, mosi, miso) spi inputs (sck, mosi, miso, ss ) t fm t fs ? ? 50 2.0 ns s 1. diagram numbers refer to dimensions in figure 13-8. spi master timing and figure 13-9. spi slave timing . 2. v dd = 5 v 10%; v ss = 0 vdc, t a = t l to t h , unless otherwise noted 3. signal production depends on software. 4. time to data active from high-impedance state 5. hold time to high-impedance state 6. with 200 pf on all spi pins. 7. 20% of v dd to 70% of v dd ; c l = 200 pf 8. 70% of v dd to 20% of v dd ; c l = 200 pf diagram number (1) characteristic (2) symbol min max unit f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hsc705c8a mc68hc705c8a ? rev. 3 technical data motorola mc68hsc705c8a a.8 3.3-volt high-speed spi timing diagram number (1) characteristic (2) symbol min max unit operating frequency master slave f op(s) f op(s) dc dc 0.5 2.1 f op mhz 1 cycle time master slave t cyc(m) t cyc(s) 2.0 480 ? ? t cyc ns 2 enable lead time master slave t lead(m) t lead(s) note (3) 240 ? ? ns 3 enable lag time master slave t lag(m) t lag(s) note (2) 720 ? ? ns 4 clock (sck) high time master slave t w(sckh)m t w(sckh)s 340 190 ? ? ns 5 clock (sck) low time master slave t w(sckl)m t w(sckl)s 340 190 ? ? ns 6 data setup time (inputs) master slave t su(m) t su(s) 100 100 ? ? ns 7 data hold time (inputs) master slave t h(m) t h(s) 100 100 ? ? ns 8 access time (4) slave t a 0 120 ns 9 disable time (5) slave t dis ? 240 ns 10 data valid time master (before capture edge) slave (after enable edge) (6) t v(m) t v(s) 0.25 ? ? 240 t cyc(m) ns continued f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data mc68hc705c8a ? rev. 3 208 mc68hsc705c8a mc68hsc705c8a 11 data hold time (outputs) master (after capture edge) slave (after enable edge) t ho(m) t ho(s) 0.25 0 ? ? t cyc(m) ns 12 rise time (7) spi outputs (sck, mosi, miso) spi inputs (sck, mosi, miso, ss ) t rm t rs ? ? 100 2.0 ns s 13 fall time (8) spi outputs (sck, mosi, miso) spi inputs (sck, mosi, miso, ss ) t fm t fs ? ? 100 2.0 ns s 1. diagram numbers refer to dimensions in figure 13-8. spi master timing and figure 13-9. spi slave timing . 2. v dd = 3.3 v 10%; v ss = 0 vdc, t a = t l to t h , unless otherwise noted 3. signal production depends on software. 4. time to data active from high-impedance state 5. hold time to high-impedance state 6. with 200 pf on all spi pins 7. 20% of v dd to 70% of v dd ; c l = 200 pf 8. 70% of v dd to 20% of v dd ; c l = 200 pf diagram number (1) characteristic (2) symbol min max unit f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hsc705c8a mc68hc705c8a ? rev. 3 technical data motorola mc68hsc705c8a a.9 ordering information table a-2 provides ordering information for the mc68hsc705c8a. table a-2. mc68hsc705c8a order numbers package type temperature range order number 40-pin plastic dual in-line package (pdip) ? 40 c to +85 c mc68hsc705c8ac (1) p (2) 44-lead plastic-leaded chip carrier (plcc) ? 40 c to +85 c mc68hsc705c8acfn (3) 44-lead ceramic-leaded chip carrier (clcc) ? 40 c to +85 c mc68hsc705c8acfs (4) 40-pin ceramic dip (cerdip) ? 40 c to +85 c mc68hsc705c8acs (5) 44-pin quad flat pack (qfp) ? 40 c to +85 c mc68hsc705c8acfb (6) 42-pin shrink dual in-line package (sdip) ? 40 c to +85 c mc68hsc705c8acb (7) 1. c = extended temperature range ( ? 40 c to +85 c) 2. p = plastic dual in-line package (pdip) 3. fn = plastic-leaded chip carrier (plcc) 4. fs = ceramic-leaded chip carrier (clcc) 5. s = windowed ceramic dual in-line package (cerdip) 6. fb = quad flat pack (qfp) 7. b = shrink dual in-line package (sdip) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data mc68hc705c8a ? rev. 3 210 mc68hsc705c8a mc68hsc705c8a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc705c8a ? rev. 3 technical data motorola index technical data ? mc68hc705c8a index a accumulator (a) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45, 154, 155, 158 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 arithmetic/logic unit (alu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 b block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 bootloader rom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 c c bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 condition code register (ccr) . . . . . . . . . . . . . . . . . . . . . . . . . . 47, 160 cop watchdog (non-programmable) diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 in stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 timeout period formula . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 when clock monitor enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 cop watchdog (programmable) cop control register (copcr) . . . . . . . . . . . . . . . . . . . . . . . . . . 64 cop reset register (coprst) . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 in stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 timeout period selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data mc68hc705c8a ? rev. 3 212 index index cpu instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 instruction types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 opcode map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155, 158, 163 accumulator (a) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154, 155, 158 condition code register (ccr) . . . . . . . . . . . . . . . . . . . . . . . . . . 160 index register (x) . . . . . . . . . . . . . . . . . . . . . . . . 154, 155, 156, 158 program counter (pc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157, 160 d data-retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 e electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 power considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 electrical specifications (high-speed part) control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 spi timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 eprom/otprom (prom) . . . . . . . . . . . . . . . . . . . . . . . . . . . 37, 103 control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 eprom erasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 mask option register 1 (mor1) . . . . . . . . . . . . . . . . . . . . . . . . . 117 mask option register 2 (mor2) . . . . . . . . . . . . . . . . . . . . . . . . . 118 option register (option) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 preprogramming steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 program register (prog) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 mc68hc05pgmr programmer board . . . . . . . . . . . . . . . . . 104 programming circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . index mc68hc705c8a ? rev. 3 technical data motorola index programming flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 programming routines . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108, 111 f f eatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 h high-speed part (mc68hsc705c8a) . . . . . . . . . . . . . . . . . . . . . . . 201 i i/o . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36, 77 data direction register a (ddra) . . . . . . . . . . . . . . . . . . . . . . . . . 79 data direction register b (ddrb) . . . . . . . . . . . . . . . . . . . . . . . . . 82 data direction register c (ddrc) . . . . . . . . . . . . . . . . . . . . . . . . . 86 port a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 port a data register (porta) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 port a i/o logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 port a pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 port b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 port b data register (portb) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 port b i/o logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 port b pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 port c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 port c data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 port c i/o logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 port c pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 port d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 i/o bits c bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 i/o register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 index register (x) . . . . . . . . . . . . . . . . . . . . . . . . 45, 154, 155, 156, 158 instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 instruction types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 opcode map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data mc68hc705c8a ? rev. 3 214 index index interrupt processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 reset/interrupt vector addresses . . . . . . . . . . . . . . . . . . . . . . . . . . 57 stacking order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 interrupts external interrupt (irq) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 internal function diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 masking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 port b interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 enabling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 port b i/o logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 sci interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 software interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 spi interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 timer interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 irq pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 j junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 l low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 data-retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 stop mode non-programmable cop in stop mode flowchart . . . . . . . . . . 74 non-programmable cop watchdog in stop mode . . . . . . . . . . 73 programmable cop in stop mode flowchart . . . . . . . . . . . . . . 72 programmable cop watchdog in stop mode . . . . . . . . . . . . . 71 sci during stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 spi during stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 stop/wait mode function flowchart . . . . . . . . . . . . . . . . . . . . . . 70 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 non-programmable cop watchdog in wait mode . . . . . . . . . . 75 programmable cop watchdog in wait mode . . . . . . . . . . . . . 75 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . index mc68hc705c8a ? rev. 3 technical data motorola index m mask option registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23, 117, 118 mc68hsc705c8a (high-speed part) . . . . . . . . . . . . . . . . . . . . . . . 201 control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 dc electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 programmable cop timeout period selection . . . . . . . . . . . . . . 202 spi timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 mechanical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 memory bootloader rom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 i/o . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 i/o register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35, 38 prom (eprom/otprom) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 ram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35, 38 o on-chip memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 opcode map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 option register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 order numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 osc1 pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 osc2 pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 oscillator ceramic resonator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 crystal resonator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 external clock signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data mc68hc705c8a ? rev. 3 216 index index p pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 port a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33, 78 data direction register a (ddra) . . . . . . . . . . . . . . . . . . . . . . . . . 79 port a data register (port a) . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 port a i/o logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 port a pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 port b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33, 81 data direction register b (ddrb) . . . . . . . . . . . . . . . . . . . . . . . . . 82 port b data register (portb) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 port b i/o logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 port b pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 port c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33, 85 data direction register c (ddrc) . . . . . . . . . . . . . . . . . . . . . . . . . 86 port c data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 port c i/o logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 port c pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 port d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33, 88 power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 program counter (pc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46, 157, 160 programmable options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 prom (eprom/otprom) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 r ram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 registers i/o register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 reset and interrupt processing flowchart . . . . . . . . . . . . . . . . . . . . . . 59 reset pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 clock monitor reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65, 67 with stop instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . index mc68hc705c8a ? rev. 3 technical data motorola index cop watchdog resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 non-programmable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 non-programmable cop watchdog diagram . . . . . . . . . . . . . 67 programmable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 programmable cop watchdog diagram . . . . . . . . . . . . . . . . . 63 enabling both programmable and non-programmable cops . . . 65 external reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 power-on reset (por) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 reset sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 rom (bootloader) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 s serial communications interface (sci) . . . . . . . . . . . . . . . . . . . . . . . 121 baud rate generator clock prescaling . . . . . . . . . . . . . . . . . . . . . 136 baud rate register (baud) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 baud rate selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 baud rate selection examples . . . . . . . . . . . . . . . . . . . . . . . . . . 138 during stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 sci control register 1 (sccr1) . . . . . . . . . . . . . . . . . . . . . . . . . 130 sci control register 2 (sccr2) . . . . . . . . . . . . . . . . . . . . . . . . . 131 sci data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 sci data register (scdr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 sci i/o registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 sci interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 sci operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 sci receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 sci status register (scsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 sci transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 serial peripheral interface (spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 during stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 master/slave connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 multiple-spi systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 pin functions in master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 pin functions in slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 serial clock polarity and phase . . . . . . . . . . . . . . . . . . . . . . . . . . 146 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data mc68hc705c8a ? rev. 3 218 index index spi block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 spi clock/data timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 spi control register (spcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 spi data register (spdr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 spi error conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 spi i/o register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 spi i/o registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 spi interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 spi operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 spi status register (spsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 stack pointer (sp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 stop mode non-programmable cop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 non-programmable cop flowchart . . . . . . . . . . . . . . . . . . . . . . . . 74 programmable cop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 programmable cop flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 sci during stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 spi during stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 stop/wait mode function flowchart . . . . . . . . . . . . . . . . . . . . . . . . 70 t tcap pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 tcmp pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 thermal resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 alternate timer registers (atrh and atrl) . . . . . . . . . . . . . . . . . 99 i/o registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 input capture registers (icrh and icrl) . . . . . . . . . . . . . . . . . . 100 output compare registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 timer control register (tcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 timer i/o register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 timer interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 timer operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 timer registers (trh and trl) . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 timer status register (tsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . index mc68hc705c8a ? rev. 3 technical data motorola index v v dd pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 v ss pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 v pp pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 w wait mode non-programmable cop watchdog in wait mode . . . . . . . . . . . . 75 programmable cop watchdog in wait mode . . . . . . . . . . . . . . . . 75 stop/wait mode function flowchart . . . . . . . . . . . . . . . . . . . . . . . . 70 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical data mc68hc705c8a ? rev. 3 220 index index f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc705c8a/d f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . |
Price & Availability of M68HC0513
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